diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala
index 2d3b118..9e8e26e 100644
--- a/src/main/scala/tilelink/Coalescing.scala
+++ b/src/main/scala/tilelink/Coalescing.scala
@@ -185,7 +185,7 @@ class CoalShiftQueue[T <: Data](
     if (i == -1) true.B else if (i == entries) false.B else mask(i)
   }
   def paddedUsed = pad({ i: Int => used(i) })
-  def validAfterInv(i: Int) = valid(i) && !io.invalidate.bits(i)
+  def validAfterInv(i: Int) = valid(i) && (!io.invalidate.valid || !io.invalidate.bits(i))
 
   val shift = (used =/= 0.U) && (io.queue.deq.ready || !validAfterInv(0))
   for (i <- 0 until entries) {
@@ -598,7 +598,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
       numPerLaneReqs,
       sourceWidth,
       offsetBits,
-      config.SizeEnum.getWidth
+      config.SizeEnum
     )
   )
   println(s"=========== table sourceWidth: ${sourceWidth}")
@@ -617,7 +617,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
       r.valid := false.B
       r.source := origReqs(i).source
       r.offset := (origReqs(i).address % (1 << config.MAX_SIZE).U) >> config.WORD_WIDTH
-      r.sizeEnum := config.SizeEnum.logSizeToEnum(origReqs(i).size).asUInt
+      r.sizeEnum := config.SizeEnum.logSizeToEnum(origReqs(i).size)
     }
   }
   newEntry.lanes(0).reqs(0).valid := true.B
@@ -753,7 +753,7 @@ class UncoalescingUnit(config: CoalescerConfig) extends Module {
       when(inflightTable.io.lookup.valid && oldReq.valid) {
         ioOldReq.valid := oldReq.valid
         ioOldReq.bits.source := oldReq.source
-        val logSize = config.SizeEnum.enumToLogSize(config.SizeEnum(oldReq.sizeEnum))
+        val logSize = found.sizeEnumT.enumToLogSize(oldReq.sizeEnum)
         ioOldReq.bits.size := logSize
         ioOldReq.bits.data :=
           getCoalescedDataChunk(
@@ -780,7 +780,7 @@ class InflightCoalReqTable(config: CoalescerConfig) extends Module {
     config.DEPTH,
     log2Ceil(config.NUM_OLD_IDS),
     config.MAX_SIZE,
-    config.SizeEnum.getWidth
+    config.SizeEnum
   )
 
   val entries = config.NUM_NEW_IDS
@@ -810,7 +810,7 @@ class InflightCoalReqTable(config: CoalescerConfig) extends Module {
           r.valid := false.B
           r.source := 0.U
           r.offset := 0.U
-          r.sizeEnum := config.SizeEnum.INVALID.asUInt
+          r.sizeEnum := config.SizeEnum.INVALID
         }
       }
     }
@@ -858,14 +858,14 @@ class InflightCoalReqTableEntry(
     val numPerLaneReqs: Int,
     val sourceWidth: Int,
     val offsetBits: Int,
-    val sizeEnumBits: Int
+    val sizeEnumT: InFlightTableSizeEnum
 ) extends Bundle {
   class PerCoreReq extends Bundle {
     val valid = Bool() // FIXME: delete this
     // FIXME: oldId and newId shares the same width
     val source = UInt(sourceWidth.W)
     val offset = UInt(offsetBits.W)
-    val sizeEnum = UInt(sizeEnumBits.W)
+    val sizeEnum = sizeEnumT()
   }
   class PerLane extends Bundle {
     val reqs = Vec(numPerLaneReqs, new PerCoreReq)
diff --git a/src/test/scala/coalescing/CoalescingUnitTest.scala b/src/test/scala/coalescing/CoalescingUnitTest.scala
index bbb54d3..0a965b6 100644
--- a/src/test/scala/coalescing/CoalescingUnitTest.scala
+++ b/src/test/scala/coalescing/CoalescingUnitTest.scala
@@ -26,7 +26,7 @@ class MultiPortQueueUnitTest extends AnyFlatSpec with ChiselScalatestTester {
         for (_ <- 0 until 100) {
           c.clock.step()
         }
-        // c.io.deq(0).valid.expect(false.B)
+      // c.io.deq(0).valid.expect(false.B)
       }
   }
 }
@@ -257,7 +257,7 @@ class CoalShiftQueueTest extends AnyFlatSpec with ChiselScalatestTester {
   }
 
   it should "dequeue invalidated entries by itself" in {
-    test(new CoalShiftQueue(UInt(8.W), 4)) { c =>
+    test(new CoalShiftQueue(gen = UInt(8.W), entries = 4)) { c =>
       c.io.invalidate.valid.poke(false.B)
 
       // prepare
@@ -266,12 +266,10 @@ class CoalShiftQueueTest extends AnyFlatSpec with ChiselScalatestTester {
       c.io.queue.enq.valid.poke(true.B)
       c.io.queue.enq.bits.poke(0x12.U)
       c.clock.step()
-      c.io.queue.deq.ready.poke(false.B)
       c.io.queue.enq.ready.expect(true.B)
       c.io.queue.enq.valid.poke(true.B)
       c.io.queue.enq.bits.poke(0x34.U)
       c.clock.step()
-      c.io.queue.deq.ready.poke(false.B)
       c.io.queue.enq.ready.expect(true.B)
       c.io.queue.enq.valid.poke(true.B)
       c.io.queue.enq.bits.poke(0x56.U)
@@ -281,12 +279,13 @@ class CoalShiftQueueTest extends AnyFlatSpec with ChiselScalatestTester {
       // invalidate two entries at head
       c.io.invalidate.valid.poke(true.B)
       c.io.invalidate.bits.poke(0x3.U)
+      // [ 0x56 | 0x34(inv) | 0x12(inv) ]
       c.clock.step()
-      // 0x12 should have been dequeued now
+      // [ 0x56 | 0x34(inv) ]
       c.io.invalidate.valid.poke(false.B)
       c.io.queue.deq.ready.poke(false.B)
       c.clock.step()
-      // 0x34 should have been dequeued now
+      // [ 0x56 ]
       c.io.queue.deq.ready.poke(true.B)
       c.io.queue.deq.valid.expect(true.B)
       c.io.queue.deq.bits.expect(0x56.U)
@@ -358,25 +357,26 @@ class UncoalescingUnitTest extends AnyFlatSpec with ChiselScalatestTester {
     // .withAnnotations(Seq(VcsBackendAnnotation))
     { c =>
       val sourceId = 0.U
+      val four = c.io.newEntry.sizeEnumT.FOUR
       c.io.coalReqValid.poke(true.B)
       c.io.newEntry.source.poke(sourceId)
       c.io.newEntry.lanes(0).reqs(0).valid.poke(true.B)
       c.io.newEntry.lanes(0).reqs(0).source.poke(1.U)
       c.io.newEntry.lanes(0).reqs(0).offset.poke(1.U)
-      c.io.newEntry.lanes(0).reqs(0).sizeEnum.poke(1.U) // 1.U is FOUR
+      c.io.newEntry.lanes(0).reqs(0).sizeEnum.poke(four)
       c.io.newEntry.lanes(0).reqs(1).valid.poke(true.B)
       c.io.newEntry.lanes(0).reqs(1).source.poke(2.U)
       c.io.newEntry.lanes(0).reqs(1).offset.poke(0.U)
-      c.io.newEntry.lanes(0).reqs(1).sizeEnum.poke(1.U)
+      c.io.newEntry.lanes(0).reqs(1).sizeEnum.poke(four)
       c.io.newEntry.lanes(1).reqs(0).valid.poke(false.B)
       c.io.newEntry.lanes(2).reqs(0).valid.poke(true.B)
       c.io.newEntry.lanes(2).reqs(0).source.poke(2.U)
       c.io.newEntry.lanes(2).reqs(0).offset.poke(2.U)
-      c.io.newEntry.lanes(2).reqs(0).sizeEnum.poke(1.U)
+      c.io.newEntry.lanes(2).reqs(0).sizeEnum.poke(four)
       c.io.newEntry.lanes(2).reqs(1).valid.poke(true.B)
       c.io.newEntry.lanes(2).reqs(1).source.poke(2.U)
       c.io.newEntry.lanes(2).reqs(1).offset.poke(3.U)
-      c.io.newEntry.lanes(2).reqs(1).sizeEnum.poke(1.U)
+      c.io.newEntry.lanes(2).reqs(1).sizeEnum.poke(four)
       c.io.newEntry.lanes(3).reqs(0).valid.poke(false.B)
 
       c.clock.step()
@@ -421,7 +421,13 @@ class CoalInflightTableUnitTest extends AnyFlatSpec with ChiselScalatestTester {
   val sizeBits = 2
 
   val inflightCoalReqTableEntry =
-    new InflightCoalReqTableEntry(numLanes, numPerLaneReqs, sourceWidth, offsetBits, sizeBits)
+    new InflightCoalReqTableEntry(
+      numLanes,
+      numPerLaneReqs,
+      sourceWidth,
+      offsetBits,
+      testConfig.SizeEnum
+    )
 
   // it should "stop enqueueing when full" in {
   //   test(new InflightCoalReqTable(numLanes, sourceWidth, entries)) { c =>