From be0fcbd23bca69625c739e512041831cc73f0afa Mon Sep 17 00:00:00 2001 From: Vamber Yang Date: Tue, 2 May 2023 14:01:19 -0700 Subject: [PATCH] Support for more realistic MemTracer step 1, allow Chisel MemTracer to input read_cycle to Verilog blackbox --- src/main/resources/vsrc/SimMemTrace.v | 4 +++- src/main/scala/tilelink/Coalescing.scala | 11 ++++++++++- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/main/resources/vsrc/SimMemTrace.v b/src/main/resources/vsrc/SimMemTrace.v index 1fc858a..ab99b70 100644 --- a/src/main/resources/vsrc/SimMemTrace.v +++ b/src/main/resources/vsrc/SimMemTrace.v @@ -28,6 +28,8 @@ module SimMemTrace #(parameter FILENAME = "undefined", NUM_LANES = 4) ( input clock, input reset, + // Chisel module needs to tell Verilog blackbox which cycle to read + input [64-1:0] trace_read_cycle, // These have to match the IO port name of the Chisel wrapper module. input trace_read_ready, output [NUM_LANES-1:0] trace_read_valid, @@ -117,7 +119,7 @@ module SimMemTrace #(parameter FILENAME = "undefined", NUM_LANES = 4) ( // Since parsed results are latched to the output on the next // cycle due to staging registers, we need to pass in the next cycle // to sync up. - next_cycle_counter, + trace_read_cycle, // the left replace next_cycle_counter, tid, __in_valid[tid], diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala index 51b5ed4..08f118d 100644 --- a/src/main/scala/tilelink/Coalescing.scala +++ b/src/main/scala/tilelink/Coalescing.scala @@ -1049,10 +1049,18 @@ class TraceLine extends Bundle with HasTraceLine { class MemTraceDriverImp(outer: MemTraceDriver, config: CoalescerConfig, traceFile: String) extends LazyModuleImp(outer) with UnitTestModule { + + val globalClkCounter = RegInit(0.U(64.W)) + val traceReadCycle = RegInit(0.U(64.W)) + globalClkCounter := globalClkCounter + 1.U + traceReadCycle := traceReadCycle + 1.U + val sim = Module(new SimMemTrace(traceFile, config.numLanes)) sim.io.clock := clock sim.io.reset := reset.asBool - sim.io.trace_read.ready := true.B + // , change ready to be base on down stream + sim.io.trace_read.ready := true.B + sim.io.trace_read.cycle := traceReadCycle // Split output of SimMemTrace, which is flattened across all lanes, // back to each lane's. @@ -1195,6 +1203,7 @@ class SimMemTrace(filename: String, numLanes: Int) // Chisel can't interface with Verilog 2D port, so flatten all lanes into // single wide 1D array. // TODO: assumes 64-bit address. + val cycle = Input(UInt(64.W)) val address = Output(UInt((addrW * numLanes).W)) val is_store = Output(UInt(numLanes.W)) val size = Output(UInt((sizeW * numLanes).W))