diff --git a/radiance.mk b/radiance.mk index 196cf22..344ee54 100644 --- a/radiance.mk +++ b/radiance.mk @@ -13,7 +13,6 @@ RADPIE_BUILD_DIR = $(RADPIE_SRC_DIR)/target/release EXTRA_SIM_LDFLAGS += -L$(RADPIE_BUILD_DIR) -Wl,-rpath,$(RADPIE_BUILD_DIR) -lradpie EXTRA_SIM_PREPROC_DEFINES += \ +define+SIMULATION \ - +define+SV_DPI \ +define+GPR_RESET \ +define+LSU_DUP_DISABLE \ +define+DBG_TRACE_CORE_PIPELINE_VCS \ diff --git a/src/main/resources/vsrc/vortex b/src/main/resources/vsrc/vortex index d3e0f18..85213d2 160000 --- a/src/main/resources/vsrc/vortex +++ b/src/main/resources/vsrc/vortex @@ -1 +1 @@ -Subproject commit d3e0f18fd54e2bd0b1d7744df89a6555df0366c4 +Subproject commit 85213d287674be2b0a57ef9e4908bfd183d92802 diff --git a/src/main/scala/radiance/subsystem/Configs.scala b/src/main/scala/radiance/subsystem/Configs.scala index 1a1256d..a8acd25 100644 --- a/src/main/scala/radiance/subsystem/Configs.scala +++ b/src/main/scala/radiance/subsystem/Configs.scala @@ -263,3 +263,9 @@ class WithExtGPUMem(address: BigInt = BigInt("0x100000000", 16), }) case class GPUMemParams(address: BigInt = BigInt("0x100000000", 16), size: BigInt = 0x80000000) case class GPUMemory() extends Field[Option[GPUMemParams]](None) + +object RadianceSimArgs extends Field[Option[Boolean]](None) + +class WithRadianceSimParams(enabled: Boolean) extends Config((_, _, _) => { + case RadianceSimArgs => Some(enabled) +}) diff --git a/src/main/scala/radiance/tile/RadianceTile.scala b/src/main/scala/radiance/tile/RadianceTile.scala index 80fad66..ea377cb 100644 --- a/src/main/scala/radiance/tile/RadianceTile.scala +++ b/src/main/scala/radiance/tile/RadianceTile.scala @@ -16,7 +16,7 @@ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import org.chipsalliance.cde.config._ import radiance.memory._ -import radiance.subsystem.{GPUMemParams, GPUMemory} +import radiance.subsystem.{GPUMemParams, GPUMemory, RadianceSimArgs} case class RadianceTileParams( core: VortexCoreParams = VortexCoreParams(), @@ -183,10 +183,14 @@ class RadianceTile private ( // memory requests so that Chisel and Verilog are in agreement on bitwidths. // See VX_gpu_pkg.sv val NW_WIDTH = (if (numWarps == 1) 1 else log2Ceil(numWarps)) - val UUID_WIDTH = 44 + val UUID_WIDTH = p(RadianceSimArgs) match { + case Some(true) => 44 + case Some(false) => 1 + case None => 1 + } val imemTagWidth = UUID_WIDTH + NW_WIDTH - val LSUQ_SIZE = 8 * (numCoreLanes / numLsuLanes) + val LSUQ_SIZE = 2 * numWarps * (numCoreLanes / numLsuLanes) val LSUQ_TAG_BITS = log2Ceil(LSUQ_SIZE) + 1 /*DCACHE_BATCH_SEL_BITS*/ val dmemTagWidth = UUID_WIDTH + LSUQ_TAG_BITS // dmem and smem shares the same tag width, DCACHE_NOSM_TAG_WIDTH diff --git a/src/main/scala/radiance/tile/VortexCore.scala b/src/main/scala/radiance/tile/VortexCore.scala index b10ac58..adb10a3 100644 --- a/src/main/scala/radiance/tile/VortexCore.scala +++ b/src/main/scala/radiance/tile/VortexCore.scala @@ -234,7 +234,7 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters) addResource("/vsrc/vortex/hw/rtl/libs/VX_cyclic_arbiter.sv") // unused addResource("/vsrc/vortex/hw/rtl/libs/VX_divider.sv") addResource("/vsrc/vortex/hw/rtl/libs/VX_dp_ram.sv") - // addResource("/vsrc/vortex/hw/rtl/libs/VX_elastic_adapter.sv") + addResource("/vsrc/vortex/hw/rtl/libs/VX_elastic_adapter.sv") addResource("/vsrc/vortex/hw/rtl/libs/VX_elastic_buffer.sv") addResource("/vsrc/vortex/hw/rtl/libs/VX_fair_arbiter.sv") addResource("/vsrc/vortex/hw/rtl/libs/VX_fifo_queue.sv") @@ -247,7 +247,7 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters) // addResource("/vsrc/vortex/hw/rtl/libs/VX_mem_adapter.sv") addResource("/vsrc/vortex/hw/rtl/libs/VX_mem_rsp_sel.sv") addResource("/vsrc/vortex/hw/rtl/libs/VX_mem_scheduler.sv") - // addResource("/vsrc/vortex/hw/rtl/libs/VX_multiplier.sv") + addResource("/vsrc/vortex/hw/rtl/libs/VX_multiplier.sv") // addResource("/vsrc/vortex/hw/rtl/libs/VX_mux.sv") addResource("/vsrc/vortex/hw/rtl/libs/VX_onehot_encoder.sv") // unused addResource("/vsrc/vortex/hw/rtl/libs/VX_onehot_mux.sv") @@ -267,8 +267,8 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters) // they cause elaboration errors // addResource("/vsrc/vortex/hw/rtl/libs/VX_scope_switch.sv") // addResource("/vsrc/vortex/hw/rtl/libs/VX_scope_tap.sv") - // addResource("/vsrc/vortex/hw/rtl/libs/VX_serial_div.sv") - // addResource("/vsrc/vortex/hw/rtl/libs/VX_serial_mul.sv") + addResource("/vsrc/vortex/hw/rtl/libs/VX_serial_div.sv") + addResource("/vsrc/vortex/hw/rtl/libs/VX_serial_mul.sv") addResource("/vsrc/vortex/hw/rtl/libs/VX_shift_register.sv") addResource("/vsrc/vortex/hw/rtl/libs/VX_skid_buffer.sv") addResource("/vsrc/vortex/hw/rtl/libs/VX_sp_ram.sv") @@ -276,8 +276,8 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters) addResource("/vsrc/vortex/hw/rtl/libs/VX_stream_switch.sv") addResource("/vsrc/vortex/hw/rtl/libs/VX_stream_xbar.sv") - addResource("/vsrc/vortex/hw/dpi/float_dpi.cpp") - addResource("/vsrc/vortex/hw/dpi/float_dpi.vh") + // addResource("/vsrc/vortex/hw/dpi/float_dpi.cpp") + // addResource("/vsrc/vortex/hw/dpi/float_dpi.vh") addResource("/vsrc/vortex/hw/dpi/util_dpi.cpp") addResource("/vsrc/vortex/hw/dpi/util_dpi.vh") // needed dpi cpp files @@ -302,18 +302,18 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters) addResource("/csrc/softfloat/RISCV/specialize.h") // fpu - addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_class.sv") - addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_cvt.sv") + // addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_class.sv") + // addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_cvt.sv") addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_define.vh") - addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_div.sv") - addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_dpi.sv") - addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_dsp.sv") - addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_fma.sv") + // addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_div.sv") + // addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_dpi.sv") + // addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_dsp.sv") + // addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_fma.sv") addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_fpnew.sv") - addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_ncomp.sv") + // addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_ncomp.sv") addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_pkg.sv") - addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_rounding.sv") - addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_sqrt.sv") + // addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_rounding.sv") + // addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_sqrt.sv") addResource("/vsrc/vortex/hw/rtl/fpu/VX_fpu_to_csr_if.sv") addResource("/vsrc/vortex/hw/rtl/core/VX_fpu_unit.sv") @@ -321,6 +321,12 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters) // compile order matters; package definitions (ex. fpnew_pkg) should be // compiled before all the other modules that reference them. They are added // to vcs.mk + addResource("/vsrc/vortex/third_party/fpnew/src/common_cells/include/common_cells/registers.svh") + addResource("/vsrc/vortex/third_party/fpnew/src/fpnew_pkg.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/common_cells/src/cf_math_pkg.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/common_cells/src/cb_filter_pkg.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/common_cells/src/ecc_pkg.sv") + addResource("/vsrc/vortex/third_party/fpnew/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv") addResource("/vsrc/vortex/third_party/fpnew/src/fpnew_cast_multi.sv") addResource("/vsrc/vortex/third_party/fpnew/src/fpnew_classifier.sv") addResource("/vsrc/vortex/third_party/fpnew/src/fpnew_divsqrt_multi.sv")