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TL helper methods for entry types

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This commit is contained in:
Richard Yan
2023-05-02 01:39:27 -07:00
parent 997b421c42
commit b9953e43ca
1 changed files with 24 additions and 19 deletions
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43
src/main/scala/tilelink/Coalescing.scala
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@@ -121,7 +121,7 @@ class ReqQueueEntry(sourceWidth: Int, sizeWidth: Int, addressWidth: Int, maxSize
val mask = UInt((1 << maxSize).W) // write only val mask = UInt((1 << maxSize).W) // write only
val data = UInt((8 * (1 << maxSize)).W) // write only val data = UInt((8 * (1 << maxSize)).W) // write only
def toTLA (edgeOut: TLEdgeOut): TLBundleA = { def toTLA(edgeOut: TLEdgeOut): TLBundleA = {
val (plegal, pbits) = edgeOut.Put( val (plegal, pbits) = edgeOut.Put(
fromSource = this.source, fromSource = this.source,
toAddress = this.address, toAddress = this.address,
@@ -146,6 +146,27 @@ class RespQueueEntry(sourceWidth: Int, sizeWidth: Int, maxSize: Int) extends Bun
val source = UInt(sourceWidth.W) val source = UInt(sourceWidth.W)
val data = UInt((8 * (1 << maxSize)).W) // read only val data = UInt((8 * (1 << maxSize)).W) // read only
val error = Bool() val error = Bool()
def toTLD(edgeIn: TLEdgeIn): TLBundleD = {
val apBits = edgeIn.AccessAck(
toSource = this.source,
lgSize = this.size
)
val agBits = edgeIn.AccessAck(
toSource = this.source,
lgSize = this.size,
data = this.data
)
Mux(this.op.asBool, apBits, agBits)
}
def fromTLD(bundle: TLBundleD): Unit = {
this.source := bundle.source
this.op := TLUtils.DOpcodeIsStore(bundle.opcode)
this.size := bundle.size
this.data := bundle.data
this.error := bundle.denied
}
} }
class ReqSourceGen(sourceWidth: Int) extends Module { class ReqSourceGen(sourceWidth: Int) extends Module {
@@ -640,12 +661,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
val lane = i - 1 val lane = i - 1
val respQueue = respQueues(lane) val respQueue = respQueues(lane)
val resp = Wire(respQueueEntryT) val resp = Wire(respQueueEntryT)
resp.source := tlOut.d.bits.source resp.fromTLD(tlOut.d.bits)
resp.op := TLUtils.DOpcodeIsStore(tlOut.d.bits.opcode)
resp.size := tlOut.d.bits.size
resp.data := tlOut.d.bits.data
resp.error := tlOut.d.bits.denied
// NOTE: D channel doesn't have mask
// Queue up responses that didn't get coalesced originally ("noncoalesced" responses). // Queue up responses that didn't get coalesced originally ("noncoalesced" responses).
// Coalesced (but uncoalesced back) responses will also be enqueued into the same queue. // Coalesced (but uncoalesced back) responses will also be enqueued into the same queue.
@@ -659,18 +675,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
respQueue.io.deq(respQueueNoncoalPort).ready := true.B respQueue.io.deq(respQueueNoncoalPort).ready := true.B
tlIn.d.valid := respQueue.io.deq(respQueueNoncoalPort).valid tlIn.d.valid := respQueue.io.deq(respQueueNoncoalPort).valid
val respHead = respQueue.io.deq(respQueueNoncoalPort).bits tlIn.d.bits := respQueue.io.deq(respQueueNoncoalPort).bits.toTLD(edgeIn)
val apBits = edgeIn.AccessAck(
toSource = respHead.source,
lgSize = respHead.size
)
val agBits = edgeIn.AccessAck(
toSource = respHead.source,
lgSize = respHead.size,
data = respHead.data
)
val respBits = Mux(respHead.op.asBool, apBits, agBits)
tlIn.d.bits := respBits
// Debug only // Debug only
val inflightCounter = RegInit(UInt(32.W), 0.U) val inflightCounter = RegInit(UInt(32.W), 0.U)