From b9953e43cacc27f58fe46f7d9a0de06470864c5e Mon Sep 17 00:00:00 2001
From: Richard Yan <yrh@berkeley.edu>
Date: Tue, 2 May 2023 01:39:27 -0700
Subject: [PATCH] TL helper methods for entry types

---
 src/main/scala/tilelink/Coalescing.scala | 43 +++++++++++++-----------
 1 file changed, 24 insertions(+), 19 deletions(-)

diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala
index 3cab524..51b5ed4 100644
--- a/src/main/scala/tilelink/Coalescing.scala
+++ b/src/main/scala/tilelink/Coalescing.scala
@@ -121,7 +121,7 @@ class ReqQueueEntry(sourceWidth: Int, sizeWidth: Int, addressWidth: Int, maxSize
   val mask = UInt((1 << maxSize).W) // write only
   val data = UInt((8 * (1 << maxSize)).W) // write only
 
-  def toTLA (edgeOut: TLEdgeOut): TLBundleA = {
+  def toTLA(edgeOut: TLEdgeOut): TLBundleA = {
     val (plegal, pbits) = edgeOut.Put(
       fromSource = this.source,
       toAddress = this.address,
@@ -146,6 +146,27 @@ class RespQueueEntry(sourceWidth: Int, sizeWidth: Int, maxSize: Int) extends Bun
   val source = UInt(sourceWidth.W)
   val data = UInt((8 * (1 << maxSize)).W) // read only
   val error = Bool()
+
+  def toTLD(edgeIn: TLEdgeIn): TLBundleD = {
+    val apBits = edgeIn.AccessAck(
+      toSource = this.source,
+      lgSize = this.size
+    )
+    val agBits = edgeIn.AccessAck(
+      toSource = this.source,
+      lgSize = this.size,
+      data = this.data
+    )
+    Mux(this.op.asBool, apBits, agBits)
+  }
+
+  def fromTLD(bundle: TLBundleD): Unit = {
+    this.source := bundle.source
+    this.op := TLUtils.DOpcodeIsStore(bundle.opcode)
+    this.size := bundle.size
+    this.data := bundle.data
+    this.error := bundle.denied
+  }
 }
 
 class ReqSourceGen(sourceWidth: Int) extends Module {
@@ -640,12 +661,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
       val lane = i - 1
       val respQueue = respQueues(lane)
       val resp = Wire(respQueueEntryT)
-      resp.source := tlOut.d.bits.source
-      resp.op := TLUtils.DOpcodeIsStore(tlOut.d.bits.opcode)
-      resp.size := tlOut.d.bits.size
-      resp.data := tlOut.d.bits.data
-      resp.error := tlOut.d.bits.denied
-      // NOTE: D channel doesn't have mask
+      resp.fromTLD(tlOut.d.bits)
 
       // Queue up responses that didn't get coalesced originally ("noncoalesced" responses).
       // Coalesced (but uncoalesced back) responses will also be enqueued into the same queue.
@@ -659,18 +675,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
       respQueue.io.deq(respQueueNoncoalPort).ready := true.B
 
       tlIn.d.valid := respQueue.io.deq(respQueueNoncoalPort).valid
-      val respHead = respQueue.io.deq(respQueueNoncoalPort).bits
-      val apBits = edgeIn.AccessAck(
-        toSource = respHead.source,
-        lgSize = respHead.size
-      )
-      val agBits = edgeIn.AccessAck(
-        toSource = respHead.source,
-        lgSize = respHead.size,
-        data = respHead.data
-      )
-      val respBits = Mux(respHead.op.asBool, apBits, agBits)
-      tlIn.d.bits := respBits
+      tlIn.d.bits := respQueue.io.deq(respQueueNoncoalPort).bits.toTLD(edgeIn)
 
       // Debug only
       val inflightCounter = RegInit(UInt(32.W), 0.U)