Fix generating PutPartialData from toTLA
Including mask in the argument calls the method override that generates PutPartialData.
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@@ -102,7 +102,6 @@ class ReqQueueEntry(sourceWidth: Int, sizeWidth: Int, addressWidth: Int, maxSize
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toAddress = this.address,
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toAddress = this.address,
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lgSize = this.size,
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lgSize = this.size,
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data = this.data,
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data = this.data,
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mask = this.mask
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)
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)
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val (glegal, gbits) = edgeOut.Get(
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val (glegal, gbits) = edgeOut.Get(
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fromSource = this.source,
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fromSource = this.source,
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@@ -303,6 +302,11 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
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req.address := tlIn.a.bits.address
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req.address := tlIn.a.bits.address
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req.data := tlIn.a.bits.data
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req.data := tlIn.a.bits.data
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req.size := tlIn.a.bits.size
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req.size := tlIn.a.bits.size
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// FIXME: req.data is still containing TL-aligned data. This is fine if
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// we're simply passing through this data out the other end, but not if
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// the outgoing TL edge (tlOut) has different data width from the incoming
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// edge (tlIn). Possible TODO to only store the relevant portion of the
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// data, at the cost of re-aligning at the outgoing end.
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req.mask := tlIn.a.bits.mask
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req.mask := tlIn.a.bits.mask
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assert(reqQueue.io.queue.enq.ready, "reqQueue is supposed to be always ready")
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assert(reqQueue.io.queue.enq.ready, "reqQueue is supposed to be always ready")
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@@ -689,6 +693,7 @@ class InflightCoalReqTableEntry(
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object TLUtils {
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object TLUtils {
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def AOpcodeIsStore(opcode: UInt): Bool = {
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def AOpcodeIsStore(opcode: UInt): Bool = {
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// 0: PutFullData, 1: PutPartialData, 4: Get
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assert(
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assert(
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opcode === TLMessages.PutFullData || opcode === TLMessages.Get,
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opcode === TLMessages.PutFullData || opcode === TLMessages.Get,
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"unhandled TL A opcode found"
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"unhandled TL A opcode found"
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