From b48ab70e67e956b1d18fbba4b1f14231c09015e4 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Wed, 10 May 2023 00:26:25 -0700 Subject: [PATCH] Fix assertion falsely firing on invalid --- src/main/scala/tilelink/Coalescing.scala | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala index 218d36b..4de4a99 100644 --- a/src/main/scala/tilelink/Coalescing.scala +++ b/src/main/scala/tilelink/Coalescing.scala @@ -1429,11 +1429,13 @@ class MemTraceLogger( // This assert only holds true for PutFullData and not PutPartialData, // where HIGH bits in the mask may not be contiguous. - assert( - PopCount(tlIn.a.bits.mask) === (1.U << tlIn.a.bits.size), - "mask HIGH popcount do not match the TL size. " + - "Partial masks are not allowed for PutFull" - ) + when (tlIn.a.valid) { + assert( + PopCount(tlIn.a.bits.mask) === (1.U << tlIn.a.bits.size), + "mask HIGH popcount do not match the TL size. " + + "Partial masks are not allowed for PutFull" + ) + } val trailingZerosInMask = trailingZeros(tlIn.a.bits.mask) val dataW = tlIn.params.dataBits val mask = ~(~(0.U(dataW.W)) << ((1.U << tlIn.a.bits.size) * 8.U))