From b2a83c788e9b12855b2540d2d92095dabbaa570a Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Mon, 22 Jan 2024 01:54:45 -0800 Subject: [PATCH] Pass both A and D bundles to memfuzzer DPI --- src/main/resources/csrc/SimMemFuzzer.cc | 18 +++-- src/main/resources/vsrc/SimMemFuzzer.v | 66 ++++++++++++++----- src/main/scala/radiance/tile/VortexTile.scala | 16 ++--- 3 files changed, 70 insertions(+), 30 deletions(-) diff --git a/src/main/resources/csrc/SimMemFuzzer.cc b/src/main/resources/csrc/SimMemFuzzer.cc index 089f355..e8accb3 100644 --- a/src/main/resources/csrc/SimMemFuzzer.cc +++ b/src/main/resources/csrc/SimMemFuzzer.cc @@ -7,15 +7,23 @@ extern "C" void memfuzz_generate_rs(uint8_t *vec_a_ready, uint8_t *vec_a_valid, long long *vec_a_address, - uint8_t *vec_d_ready, uint8_t *finished); + uint8_t *vec_a_is_store, int *vec_a_size, + long long *vec_a_data, uint8_t *vec_d_ready, + uint8_t *vec_d_valid, + uint8_t *vec_d_is_store, int *vec_d_size, + uint8_t *finished); extern "C" void memfuzz_init(int num_lanes) { printf("from C: num_lanes=%d\n", num_lanes); } extern "C" void memfuzz_generate(uint8_t *vec_a_ready, uint8_t *vec_a_valid, - long long *vec_a_address, uint8_t *vec_d_ready, - uint8_t *finished) { - memfuzz_generate_rs(vec_a_ready, vec_a_valid, vec_a_address, vec_d_ready, - finished); + long long *vec_a_address, + uint8_t *vec_a_is_store, int *vec_a_size, + long long *vec_a_data, uint8_t *vec_d_ready, + uint8_t *vec_d_valid, uint8_t *vec_d_is_store, + int *vec_d_size, uint8_t *finished) { + memfuzz_generate_rs(vec_a_ready, vec_a_valid, vec_a_address, vec_a_is_store, + vec_a_size, vec_a_data, vec_d_ready, vec_d_valid, + vec_d_is_store, vec_d_size, finished); } diff --git a/src/main/resources/vsrc/SimMemFuzzer.v b/src/main/resources/vsrc/SimMemFuzzer.v index 79e84d6..d5a6bdb 100644 --- a/src/main/resources/vsrc/SimMemFuzzer.v +++ b/src/main/resources/vsrc/SimMemFuzzer.v @@ -13,7 +13,15 @@ import "DPI-C" function void memfuzz_generate input bit vec_a_ready[`MAX_NUM_LANES], output bit vec_a_valid[`MAX_NUM_LANES], output longint vec_a_address[`MAX_NUM_LANES], + output bit vec_a_is_store[`MAX_NUM_LANES], + output int vec_a_size[`MAX_NUM_LANES], + output longint vec_a_data[`MAX_NUM_LANES], + output bit vec_d_ready[`MAX_NUM_LANES], + input bit vec_d_valid[`MAX_NUM_LANES], + input bit vec_d_is_store[`MAX_NUM_LANES], + input int vec_d_size[`MAX_NUM_LANES], + output bit finished ); @@ -27,30 +35,47 @@ module SimMemFuzzer #(parameter NUM_LANES = 4) ( output [NUM_LANES-1:0] a_is_store, output [`SIMMEM_LOGSIZE_WIDTH*NUM_LANES-1:0] a_size, output [`SIMMEM_DATA_WIDTH*NUM_LANES-1:0] a_data, + output [NUM_LANES-1:0] d_ready, + input [NUM_LANES-1:0] d_valid, + input [NUM_LANES-1:0] d_is_store, + input [`SIMMEM_LOGSIZE_WIDTH*NUM_LANES-1:0] d_size, + // TODO: d_mask + // TODO: d_data + output finished ); + // "in": verilog->C, "out": C->verilog // need to be in ascending order to match with C indexing // C array sizes are static, so need to use MAX_NUM_LANES - bit __out_a_ready [0:`MAX_NUM_LANES-1]; - bit __in_a_valid [0:`MAX_NUM_LANES-1]; - longint __in_a_address [0:`MAX_NUM_LANES-1]; - bit __in_a_is_store [0:`MAX_NUM_LANES-1]; - reg [`SIMMEM_LOGSIZE_WIDTH-1:0] __in_a_size [0:`MAX_NUM_LANES-1]; - longint __in_a_data [0:`MAX_NUM_LANES-1]; - bit __in_d_ready [0:`MAX_NUM_LANES-1]; - bit __in_finished; + bit __out_a_ready [0:`MAX_NUM_LANES-1]; + bit __in_a_valid [0:`MAX_NUM_LANES-1]; + longint __in_a_address [0:`MAX_NUM_LANES-1]; + bit __in_a_is_store [0:`MAX_NUM_LANES-1]; + int __in_a_size [0:`MAX_NUM_LANES-1]; + longint __in_a_data [0:`MAX_NUM_LANES-1]; + bit __in_d_ready [0:`MAX_NUM_LANES-1]; + bit __out_d_valid [0:`MAX_NUM_LANES-1]; + bit __out_d_is_store [0:`MAX_NUM_LANES-1]; + int __out_d_size [0:`MAX_NUM_LANES-1]; + bit __in_finished; genvar g; generate for (g = 0; g < NUM_LANES; g = g + 1) begin assign __out_a_ready[g] = a_ready[g]; assign a_valid[g] = __in_a_valid[g]; - assign a_address[`SIMMEM_DATA_WIDTH*g +: `SIMMEM_DATA_WIDTH] = __in_a_address[g]; - + assign a_address[`SIMMEM_DATA_WIDTH*g +: `SIMMEM_DATA_WIDTH] + = __in_a_address[g][`SIMMEM_DATA_WIDTH-1:0]; assign a_is_store[g] = __in_a_is_store[g]; - assign a_size[`SIMMEM_LOGSIZE_WIDTH*g +: `SIMMEM_LOGSIZE_WIDTH] = __in_a_size[g]; - assign a_data[`SIMMEM_DATA_WIDTH*g +: `SIMMEM_DATA_WIDTH] = __in_a_data[g]; + assign a_size[`SIMMEM_LOGSIZE_WIDTH*g +: `SIMMEM_LOGSIZE_WIDTH] + = __in_a_size[g][`SIMMEM_LOGSIZE_WIDTH-1:0]; + assign a_data[`SIMMEM_DATA_WIDTH*g +: `SIMMEM_DATA_WIDTH] + = __in_a_data[g][`SIMMEM_DATA_WIDTH-1:0]; + assign d_ready[g] = __in_d_ready[g]; + assign __out_d_valid[g] = d_valid[g]; + assign __out_d_is_store[g] = d_is_store[g]; + assign __out_d_size[g] = d_size[`SIMMEM_LOGSIZE_WIDTH*g +: `SIMMEM_LOGSIZE_WIDTH]; end endgenerate assign finished = __in_finished; @@ -67,9 +92,8 @@ module SimMemFuzzer #(parameter NUM_LANES = 4) ( for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin __in_a_valid[tid] = 1'b0; __in_a_address[tid] = `SIMMEM_DATA_WIDTH'b0; - __in_a_is_store[tid] = 1'b0; - __in_a_size[tid] = `SIMMEM_LOGSIZE_WIDTH'b0; + __in_a_size[tid] = 32'b0; __in_a_data[tid] = `SIMMEM_DATA_WIDTH'b0; __in_d_ready[tid] = 1'b0; end @@ -79,15 +103,23 @@ module SimMemFuzzer #(parameter NUM_LANES = 4) ( __out_a_ready, __in_a_valid, __in_a_address, + __in_a_is_store, + __in_a_size, + __in_a_data, + __in_d_ready, + __out_d_valid, + __out_d_is_store, + __out_d_size, + __in_finished ); for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin - $display("verilog: %04d valid[%d]=%d, address[%d]=%d", - $time, tid, __in_a_valid[tid], tid, __in_a_address[tid]); + $display("verilog: %04d valid[%d]=%d, address[%d]=%d, __in_d_ready[%d]=%d", + $time, tid, __in_a_valid[tid], tid, __in_a_address[tid], tid, __in_d_ready[tid]); end - if ($time >= 32'd200000) begin + if ($time >= 64'd200000) begin $finish; end end diff --git a/src/main/scala/radiance/tile/VortexTile.scala b/src/main/scala/radiance/tile/VortexTile.scala index 10d09c1..b8f6616 100644 --- a/src/main/scala/radiance/tile/VortexTile.scala +++ b/src/main/scala/radiance/tile/VortexTile.scala @@ -178,12 +178,12 @@ class VortexTile private ( case Some(simtParam) => log2Ceil(simtParam.nSrcIds) case None => 4 } - require( - dmemSourceWidth >= 4, - "Setting a small number of sourceIds may cause correctness bug inside " + - "Vortex core due to synchronization issues in vx_wspawn. " + - "We recommend setting nSrcIds to at least 16." - ) + // require( + // dmemSourceWidth >= 4, + // "Setting a small number of sourceIds may cause correctness bug inside " + + // "Vortex core due to synchronization issues in vx_wspawn. " + + // "We recommend setting nSrcIds to at least 16." + // ) val smemSourceWidth = 4 // FIXME: hardcoded @@ -295,9 +295,9 @@ class VortexTile private ( // Conditionally instantiate memory coalescer val coalescerNode = p(CoalescerKey) match { - case Some(coalescerParam) => { + case Some(coalParam) => { val coal = LazyModule( - new CoalescingUnit(coalescerParam) + new CoalescingUnit(coalParam) ) coal.cpuNode :=* dmemAggregateNode coal.aggregateNode // N+1 lanes