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Rename arbiter config and IO

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This commit is contained in:
Hansung Kim
2023-05-06 18:36:46 -07:00
parent caa5ebf943
commit afd8a0910a
1 changed files with 13 additions and 12 deletions
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25
src/main/scala/tilelink/Coalescing.scala
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@@ -53,9 +53,10 @@ case class CoalescerConfig(
coalLogSizes: Seq[Int], // list of coalescer sizes to try in the MonoCoalescers coalLogSizes: Seq[Int], // list of coalescer sizes to try in the MonoCoalescers
// each size is log(byteSize) // each size is log(byteSize)
sizeEnum: InFlightTableSizeEnum, sizeEnum: InFlightTableSizeEnum,
numCoalReq: Int, // the total number of coalesced request numCoalReqs: Int, // total number of coalesced requests we can generate in one cycle
arbiterOutputs: Int, //total number RW ports from the numArbiterOutputPorts: Int, // total of output ports the arbiter will arbitrate into.
bankStrideInBytes: Int //cache line strides across the different banks // this has to match downstream cache's configuration
bankStrideInBytes: Int // cache line strides across the different banks
) { ) {
// maximum coalesced size // maximum coalesced size
def maxCoalLogSize: Int = coalLogSizes.max def maxCoalLogSize: Int = coalLogSizes.max
@@ -77,8 +78,8 @@ object defaultConfig extends CoalescerConfig(
respQueueDepth = 4, respQueueDepth = 4,
coalLogSizes = Seq(3), coalLogSizes = Seq(3),
sizeEnum = DefaultInFlightTableSizeEnum, sizeEnum = DefaultInFlightTableSizeEnum,
numCoalReq = 1, numCoalReqs = 1,
arbiterOutputs = 4, numArbiterOutputPorts = 4,
bankStrideInBytes = 64 //Current L2 is strided by 512 bits bankStrideInBytes = 64 //Current L2 is strided by 512 bits
) )
@@ -1729,10 +1730,10 @@ class TLRAMCoalescerTest(timeout: Int = 500000)(implicit p: Parameters) extends
class CoalArbiter(config: CoalescerConfig) (implicit p: Parameters) extends LazyModule { class CoalArbiter(config: CoalescerConfig) (implicit p: Parameters) extends LazyModule {
// Let SIMT's word size be 32, and read/write granularity be 256 // Let SIMT's word size be 32, and read/write granularity be 256
val fullSourceIdRange = config.numOldSrcIds * config.numLanes + config.numNewSrcIds * config.numCoalReq val fullSourceIdRange = config.numOldSrcIds * config.numLanes + config.numNewSrcIds * config.numCoalReqs
// K client nodes of edge size 32 for non-coalesced reqs // K client nodes of edge size 32 for non-coalesced reqs
val nonCoalNarrowNodes = Seq.tabulate(config.arbiterOutputs){ i => val nonCoalNarrowNodes = Seq.tabulate(config.numArbiterOutputPorts){ i =>
val nonCoalNarrowParam = Seq( val nonCoalNarrowParam = Seq(
TLMasterParameters.v1( TLMasterParameters.v1(
name = "NonCoalNarrowNode" + i.toString, name = "NonCoalNarrowNode" + i.toString,
@@ -1750,7 +1751,7 @@ class CoalArbiter(config: CoalescerConfig) (implicit p: Parameters) extends Lazy
) )
// K client nodes of edge size 256 for the coalesced reqs // K client nodes of edge size 256 for the coalesced reqs
val coalReqNodes = Seq.tabulate(config.arbiterOutputs){ i => val coalReqNodes = Seq.tabulate(config.numArbiterOutputPorts){ i =>
val coalParam = Seq( val coalParam = Seq(
TLMasterParameters.v1( TLMasterParameters.v1(
name = "CoalReqNode" + i.toString, name = "CoalReqNode" + i.toString,
@@ -1805,10 +1806,10 @@ class CoalArbiterImpl(outer: CoalArbiter,
val io =IO(new Bundle { val io =IO(new Bundle {
val nonCoalVec = Vec(config.numLanes, Flipped(Decoupled(nonCoalEntryT.cloneType))) val nonCoalReqs = Vec(config.numLanes, Flipped(Decoupled(nonCoalEntryT)))
val coalVec = Vec(config.numCoalReq, Flipped(Decoupled(coalEntryT.cloneType))) val coalReqs = Vec(config.numCoalReqs, Flipped(Decoupled(coalEntryT)))
val respNonCoalVec = Vec(config.numLanes, Decoupled(respNonCoalEntryT.cloneType)) val nonCoalResps = Vec(config.numLanes, Decoupled(respNonCoalEntryT))
val respCoalBundle = Decoupled(respCoalBundleT.cloneType) val coalResp = Decoupled(respCoalBundleT)
} }
) )