diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala
index 1933f33..03cdf4b 100644
--- a/src/main/scala/tilelink/Coalescing.scala
+++ b/src/main/scala/tilelink/Coalescing.scala
@@ -1511,6 +1511,8 @@ class MemTraceDriverImp(
   when(sim.io.trace_read.finished) {
     traceFinished := true.B
   }
+  io.finished := traceFinished
+
   //currently the .cc file ouptuts finished=true while it still need to issue one more request
   val noValidReqs     = sim.io.trace_read.valid === 0.U     
   val allReqReclaimed = !(sourceGens.map(_.io.inflight).reduce(_ || _))