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Fixed MemTracerDriverImpr to generate the last request when SimMemTrace outputs finished signal

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Vamber Yang
2023-05-19 05:03:13 -07:00
parent d88a734aee
commit ab3ce82aff
1 changed files with 4 additions and 2 deletions
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6
src/main/scala/tilelink/Coalescing.scala
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@@ -250,7 +250,7 @@ class RoundRobinSourceGenerator(sourceWidth: Int, ignoreInUse: Boolean = true)
// for debugging // for debugging
// also for indicating if there is at least one inflight request that hasn't been reclaimed // also for indicating if there is at least one inflight request that hasn't been reclaimed
val outstanding = RegInit(UInt((sourceWidth + 1).W), 0.U) val outstanding = RegInit(UInt((sourceWidth + 1).W), 0.U)
io.inflight := outstanding > 0.U io.inflight := (outstanding > 0.U) || io.gen
val numSourceId = 1 << sourceWidth val numSourceId = 1 << sourceWidth
// true: in use, false: available // true: in use, false: available
@@ -1475,10 +1475,12 @@ class MemTraceDriverImp(
when(sim.io.trace_read.finished) { when(sim.io.trace_read.finished) {
traceFinished := true.B traceFinished := true.B
} }
//currently the .cc file ouptuts finished=true while it still need to issue one more request
val noValidReqs = sim.io.trace_read.valid === 0.U
val allReqReclaimed = !(sourceGens.map(_.io.inflight).reduce(_ || _)) val allReqReclaimed = !(sourceGens.map(_.io.inflight).reduce(_ || _))
when(traceFinished && allReqReclaimed) { when(traceFinished && allReqReclaimed && noValidReqs) {
assert( assert(
false.B, false.B,
"\n\n\nsimulation Successfully finished\n\n\n (this assertion intentional fail upon MemTracer termination)" "\n\n\nsimulation Successfully finished\n\n\n (this assertion intentional fail upon MemTracer termination)"