From a1cdf10b20134af324ad86ba9740f2ece78e3f57 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Thu, 4 May 2023 15:33:44 -0700 Subject: [PATCH] Revert to non-synthesis TB; wip config compile error fix --- src/main/scala/tilelink/Coalescing.scala | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala index 58d48a7..fb0aef0 100644 --- a/src/main/scala/tilelink/Coalescing.scala +++ b/src/main/scala/tilelink/Coalescing.scala @@ -534,12 +534,15 @@ class MultiCoalescer(windowT: CoalShiftQueue[ReqQueueEntry], coalReqT: ReqQueueE } class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends LazyModuleImp(outer) { - assert(outer.cpuNode.in.length == config.numLanes, - s"number of incoming edges (${outer.cpuNode.in.length}) is not the same as number of lanes") - assert(outer.cpuNode.in.head._1.params.sourceBits == log2Ceil(config.numOldSrcIds), - s"old source id bits TL param (${outer.cpuNode.in.head._1.params.sourceBits}) mismatch with config") - assert(outer.cpuNode.in.head._1.params.addressBits == config.addressWidth, - s"address width TL param (${outer.cpuNode.in.head._1.params.addressBits}) mismatch with config") + require(outer.cpuNode.in.length == config.numLanes, + s"number of incoming edges (${outer.cpuNode.in.length}) is not the same as " + + s"config.numLanes (${config.numLanes})") + require(outer.cpuNode.in.head._1.params.sourceBits == log2Ceil(config.numOldSrcIds), + s"TL param sourceBits (${outer.cpuNode.in.head._1.params.sourceBits}) " + + s"mismatch with log2(config.numOldSrcIds) (${log2Ceil(config.numOldSrcIds)})") + require(outer.cpuNode.in.head._1.params.addressBits == config.addressWidth, + s"TL param addressBits (${outer.cpuNode.in.head._1.params.addressBits}) " + + s"mismatch with config.addressWidth (${config.addressWidth})") val sourceWidth = outer.cpuNode.in.head._1.params.sourceBits // note we are using word size. assuming all coalescer inputs are word sized