Set numBarriers == numWarps
still requires manually updating radiance.mk
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@@ -325,8 +325,8 @@ class RadianceTile private (
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}
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}
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// Barrier synchronization node
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// Barrier synchronization node
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// FIXME: hardcoded params
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// FIXME: hardcoded param eq
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val numBarriers = 8
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val numBarriers = numWarps
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def barrierIdBits = log2Ceil(numBarriers)
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def barrierIdBits = log2Ceil(numBarriers)
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val barrierMasterNode = BarrierMasterNode(barrierIdBits)
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val barrierMasterNode = BarrierMasterNode(barrierIdBits)
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@@ -570,7 +570,7 @@ class RadianceTileModuleImp(outer: RadianceTile)
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// make connection:
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// make connection:
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// VortexBundle <--> sourceId filter <--> VortexTLAdapter <--> dmemNodes
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// VortexBundle <--> sourceId filter <--> VortexTLAdapter <--> dmemNodes
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//
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//
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// Chisel doesn't support 2-D array in BlackBox interface to Verilog, so
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// Chisel doesn't support 2-D array in BlackBox interface to Verilog, so
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// need to flatten everything.
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// need to flatten everything.
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dmemTLAdapters.zipWithIndex.foreach {
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dmemTLAdapters.zipWithIndex.foreach {
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