diff --git a/src/main/scala/radiance/tile/RadianceTile.scala b/src/main/scala/radiance/tile/RadianceTile.scala
index 31212df..80fad66 100644
--- a/src/main/scala/radiance/tile/RadianceTile.scala
+++ b/src/main/scala/radiance/tile/RadianceTile.scala
@@ -325,8 +325,8 @@ class RadianceTile private (
   }
 
   // Barrier synchronization node
-  // FIXME: hardcoded params
-  val numBarriers = 8
+  // FIXME: hardcoded param eq
+  val numBarriers = numWarps
   def barrierIdBits = log2Ceil(numBarriers)
   val barrierMasterNode = BarrierMasterNode(barrierIdBits)
 
@@ -570,7 +570,7 @@ class RadianceTileModuleImp(outer: RadianceTile)
 
       // make connection:
       // VortexBundle <--> sourceId filter <--> VortexTLAdapter <--> dmemNodes
-      // 
+      //
       // Chisel doesn't support 2-D array in BlackBox interface to Verilog, so
       // need to flatten everything.
       dmemTLAdapters.zipWithIndex.foreach {