general cleanup

src/main/scala/radiance/memory/AddressRewriterNode.scala

@@ -2,10 +2,10 @@ package radiance.memory
 
 import chisel3._
 import chisel3.experimental.SourceInfo
-import chisel3.util._
-import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink.TLAdapterNode
 import org.chipsalliance.cde.config.Parameters
+import org.chipsalliance.diplomacy.ValName
+import org.chipsalliance.diplomacy.lazymodule._
 
 
 class AddressRewriterNode(rewriteFn: UInt => UInt)(implicit p: Parameters) extends LazyModule {

src/main/scala/radiance/memory/AlignFilterNode.scala

@@ -1,12 +1,13 @@
 package radiance.memory
 
 import chisel3._
-import chisel3.experimental.SourceInfo
 import chisel3.util._
-import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util.BundleField
+import freechips.rocketchip.diplomacy.AddressSet
 import org.chipsalliance.cde.config.Parameters
+import org.chipsalliance.diplomacy.ValName
+import org.chipsalliance.diplomacy.lazymodule._
 
 // this node splits the incoming requests into two outgoing edges,
 // the first edge contains requests that match the filter AddressSet,
@@ -19,9 +20,6 @@ class AlignFilterNode(filters: Seq[AddressSet])(implicit p: Parameters) extends
       s"found ${seq.map(_.masters.size).sum}")
     val master = seq.head.masters.head
 
-    // TODO: to implement multiple filters, source Id mapping needs to be redone
-    // assert(filters.length == 1, "multiple filters currently not supported")
-
     val in_mapping = TLXbar.mapInputIds(Seq.fill(filters.length + 1)(seq.head))
     val unaligned_src_range = in_mapping.last
 

src/main/scala/radiance/memory/DistributorNode.scala

@@ -3,10 +3,12 @@ package radiance.memory
 import chisel3._
 import chisel3.experimental.SourceInfo
 import chisel3.util._
-import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util.BundleField
 import org.chipsalliance.cde.config.Parameters
+import org.chipsalliance.diplomacy.ValName
+import org.chipsalliance.diplomacy.lazymodule._
 
 
 class DistributorNode(from: Int, to: Int)(implicit p: Parameters) extends LazyModule {

src/main/scala/radiance/memory/RWSplitterNode.scala

@@ -3,11 +3,12 @@ package radiance.memory
 import chisel3._
 import chisel3.experimental.SourceInfo
 import chisel3.util._
-import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, IdRange}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util.BundleField
 import org.chipsalliance.cde.config.Parameters
-
+import org.chipsalliance.diplomacy.ValName
+import org.chipsalliance.diplomacy.lazymodule._
 
 class RWSplitterNode(visibility: Option[AddressSet], override val name: String = "rw_splitter")
                     (implicit p: Parameters) extends LazyModule {
@@ -55,7 +56,6 @@ class RWSplitterNode(visibility: Option[AddressSet], override val name: String =
       )
     },
     managerFn = { seq =>
-      // val fifoIdFactory = TLXbar.relabeler()
       println(f"combined address range of $name managers: " +
         f"${AddressSet.unify(seq.flatMap(_.slaves.flatMap(_.address)))}, supports:" +
         f"${seq.map(_.anySupportClaims).reduce(_ mincover _)}")
@@ -152,12 +152,12 @@ class RWSplitterNode(visibility: Option[AddressSet], override val name: String =
 
 object RWSplitterNode {
   def apply()(implicit p: Parameters, valName: ValName, sourceInfo: SourceInfo): TLNexusNode = {
-    LazyModule(new RWSplitterNode(None, name = valName.name)).node
+    LazyModule(new RWSplitterNode(None, name = valName.value)).node
   }
 
   def apply(visibility: AddressSet)
            (implicit p: Parameters, valName: ValName, sourceInfo: SourceInfo): TLNexusNode = {
-    apply(visibility, valName.name)
+    apply(visibility, valName.value)
   }
 
   def apply(visibility: AddressSet, name: String)

src/main/scala/radiance/memory/Utils.scala

@@ -1,7 +1,7 @@
 package radiance.memory
 import freechips.rocketchip.tilelink._
 import org.chipsalliance.diplomacy.lazymodule._
-import org.chipsalliance.diplomacy.{DisableMonitors, ValName}
+import org.chipsalliance.diplomacy.DisableMonitors
 import org.chipsalliance.cde.config.Parameters
 
 object guardMonitors {

src/main/scala/radiance/memory/XbarWithExtPolicy.scala

@@ -2,7 +2,6 @@ package radiance.memory
 
 import chisel3._
 import chisel3.experimental.SourceInfo
-import chisel3.util.Valid
 import freechips.rocketchip.tilelink._
 import org.chipsalliance.cde.config.Parameters
 import org.chipsalliance.diplomacy.ValName

src/main/scala/radiance/tile/RadianceCluster.scala

@@ -16,8 +16,8 @@ import radiance.memory._
 import radiance.subsystem.{RadianceFrameBufferKey, RadianceSharedMemKey}
 
 case class RadianceClusterParams(
-  val clusterId: Int,
+  clusterId: Int,
-  val clockSinkParams: ClockSinkParameters = ClockSinkParameters()
+  clockSinkParams: ClockSinkParameters = ClockSinkParameters()
 ) extends InstantiableClusterParams[RadianceCluster] {
   val baseName = "radiance_cluster"
   val uniqueName = s"${baseName}_$clusterId"
@@ -32,28 +32,18 @@ class RadianceCluster (
   crossing: ClockCrossingType,
   lookup: LookupByClusterIdImpl
 )(implicit p: Parameters) extends Cluster(thisClusterParams, crossing, lookup) {
-  // Instantiate cluster-local shared memory scratchpad
+  val smemKey = p(RadianceSharedMemKey).get
-  //
+  val numCoresInCluster = leafTiles.size - gemminiTiles.size
-  // Instantiate the same number of banks as there are lanes.
 
- // must toSeq here, otherwise Iterable is lazy and will break diplomacy
+  // make the shared memory srams and interconnects
   val gemminiTiles = leafTiles.values.filter(_.isInstanceOf[GemminiTile]).toSeq.asInstanceOf[Seq[GemminiTile]]
   val radianceTiles = leafTiles.values.filter(_.isInstanceOf[RadianceTile]).toSeq.asInstanceOf[Seq[RadianceTile]]
 
   // TODO: this probably needs to be instantiated inside the radiance shared mem module
   val virgoSharedMemComponents = new VirgoSharedMemComponents(thisClusterParams, gemminiTiles, radianceTiles)
-  val sharedMemSystem = LazyModule(new RadianceSharedMem(virgoSharedMemComponents, clbus))
+  LazyModule(new RadianceSharedMem(virgoSharedMemComponents, clbus)).suggestName("shared_mem")
-
-  val numCoresInCluster = leafTiles.size - gemminiTiles.size
-
-  val smemKey = p(RadianceSharedMemKey).get
-  val wordSize = smemKey.wordSize
-  val smemBase = smemKey.address
-  val smemBanks = smemKey.numBanks
-  val smemWidth = smemKey.numWords * smemKey.wordSize
-  val smemDepth = smemKey.size / smemWidth / smemBanks
-  val smemSize = smemWidth * smemDepth * smemBanks
 
+  // direct core-accelerator connections
   val radianceAccSlaveNodes = Seq.fill(numCoresInCluster)(AccSlaveNode())
   (radianceAccSlaveNodes zip radianceTiles).foreach { case (a, r) => a := r.accMasterNode }
   val gemminiAccMasterNodes = gemminiTiles.map { tile =>
@@ -63,35 +53,22 @@ class RadianceCluster (
   }
   gemminiTiles.foreach { _.slaveNode :=* TLWidthWidget(4) :=* clbus.outwardNode }
 
-  val traceTLNode = TLAdapterNode(clientFn = c => c, managerFn = m => m)
   // printf and perf counter buffer
-  TLRAM(AddressSet(smemBase + smemSize, numCoresInCluster * 0x200 - 1)) := traceTLNode :=
+  val traceTLNode = TLAdapterNode(clientFn = c => c, managerFn = m => m)
+  TLRAM(AddressSet(smemKey.address + smemKey.size, numCoresInCluster * 0x200 - 1)) := traceTLNode :=
     TLBuffer() := TLFragmenter(4, 4) := clbus.outwardNode
 
+  // framebuffer
   p(RadianceFrameBufferKey).foreach { key =>
     val fb = LazyModule(new FrameBuffer(key.baseAddress, key.width, key.size, key.validAddress, key.fbName))
     fb.node := TLBuffer() := TLFragmenter(4, 4) := clbus.outwardNode
   }
 
-  // Diplomacy sink nodes for cluster-wide barrier sync signal
+  // barrier connections
   val barrierSlaveNode = BarrierSlaveNode(numCoresInCluster)
-
-  // HACK: This is a workaround of the CanAttachTile bus connecting API that
-  // works by downcasting tile and directly accessing the node inside that is
-  // not exposed as a master in HierarchicalElementCrossingParamsLike.
-  // val tile = leafTiles(0).asInstanceOf[RadianceTile]
-  // val perSmemPortXbars = Seq.fill(tile.smemNodes.size) { LazyModule(new TLXbar) }
-
-  // Tie corresponding smem ports from every tile into a single port using
-  // Xbars so that the number of ports going into the sharedmem do not scale
-  // with the number of tiles.
   radianceTiles.foreach { tile =>
-    // (perSmemPortXbars zip tile.smemNodes).foreach {
-    //   case (xbar, node) => xbar.node := node
-    // }
     barrierSlaveNode := tile.barrierMasterNode
   }
-  // perSmemPortXbars.foreach { clbus.inwardNode := _.node }
 
   override lazy val module = new RadianceClusterModuleImp(this)
 }
@@ -112,10 +89,6 @@ class RadianceClusterModuleImp(outer: RadianceCluster) extends ClusterModuleImp(
 
   val coreAccs = outer.radianceAccSlaveNodes.map(_.in.head._1)
   val gemminiAccs = outer.gemminiAccMasterNodes.map(_.out.head._1)
-  // val gemminiTileAcc = outer.gemminiTile.accSlaveNode.in.head._1
-
-  // gemminiTileAcc.cmd := gemminiAcc.cmd
-  // gemminiAcc.status := gemminiTileAcc.status
 
   gemminiAccs.zipWithIndex.foreach { case (g, gi) =>
     val active = coreAccs.map(acc => acc.cmd.valid && (acc.dest() === gi.U))