From 8148cc361c5e79dbe2a4d82c7212a4d6f6f8b3b1 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Fri, 3 May 2024 14:22:23 -0700 Subject: [PATCH 1/4] Add assertion on numWarps >= numLsuLanes --- src/main/scala/radiance/tile/RadianceTile.scala | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/main/scala/radiance/tile/RadianceTile.scala b/src/main/scala/radiance/tile/RadianceTile.scala index 502371e..6b0e842 100644 --- a/src/main/scala/radiance/tile/RadianceTile.scala +++ b/src/main/scala/radiance/tile/RadianceTile.scala @@ -193,9 +193,13 @@ class RadianceTile private ( } val imemTagWidth = UUID_WIDTH + NW_WIDTH - // val LSUQ_SIZE = 4 * numWarps * (numCoreLanes / numLsuLanes) - // assert(LSUQ_SIZE == p(SIMTCoreKey).get.nSrcIds) - val LSUQ_SIZE = p(SIMTCoreKey).get.nSrcIds + // val LSUQ_SIZE = p(SIMTCoreKey).get.nSrcIds + require(numWarps >= numLsuLanes, + s"Vortex core requires numWarps (${numWarps}) >= numLsuLanes (${numLsuLanes})") + val LSUQ_SIZE = 8 * (numCoreLanes / numLsuLanes) + require(LSUQ_SIZE == p(SIMTCoreKey).get.nSrcIds, + s"LSUQ_SIZE (${LSUQ_SIZE}) != nSrcIds (${p(SIMTCoreKey).get.nSrcIds})" + + " which can result in TileLink srcId underutilization") val LSUQ_TAG_BITS = log2Ceil(LSUQ_SIZE) + 1 /*DCACHE_BATCH_SEL_BITS*/ val dmemTagWidth = UUID_WIDTH + LSUQ_TAG_BITS // dmem and smem shares the same tag width, DCACHE_NOSM_TAG_WIDTH From 2bde4fa6ed1f457587908ce619539d735223be4f Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Tue, 7 May 2024 16:12:26 -0700 Subject: [PATCH 2/4] Enable tensor core in radiance.mk --- radiance.mk | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/radiance.mk b/radiance.mk index 4711c93..0617373 100644 --- a/radiance.mk +++ b/radiance.mk @@ -20,13 +20,13 @@ EXTRA_SIM_PREPROC_DEFINES += \ +define+ICACHE_DISABLE +define+DCACHE_DISABLE \ +define+GBAR_ENABLE \ +define+GBAR_CLUSTER_ENABLE \ - +define+FPU_FPNEW \ - +define+EXT_T_DISABLE \ - +define+NUM_BARRIERS=8 \ - +define+NUM_CORES=2 +define+NUM_THREADS=8 +define+NUM_WARPS=8 - # Can't increase this to above 14, since the binary accesses 0xff0040.. - # which is unmapped to any memory - # +define+SMEM_LOG_SIZE=14 \ + +define+NUM_FPU_BLOCKS=2 \ + +define+NUM_BARRIERS=4 \ + +define+NUM_LSU_LANES=4 \ + +define+NUM_CORES=1 +define+NUM_THREADS=32 +define+NUM_WARPS=4 + # +define+EXT_T_DISABLE \ + # +define+FPU_FPNEW \ + # +define+SMEM_LOG_SIZE=15 \ # cargo handles building of Rust files all on its own, so make this a PHONY # target to run cargo unconditionally From a0c7ce93d7472cd01eee7fd1408474e4fb45be74 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Tue, 7 May 2024 16:17:21 -0700 Subject: [PATCH 3/4] Add back LSUQ_SIZE logic --- src/main/scala/radiance/tile/RadianceTile.scala | 1 - 1 file changed, 1 deletion(-) diff --git a/src/main/scala/radiance/tile/RadianceTile.scala b/src/main/scala/radiance/tile/RadianceTile.scala index 6b0e842..534da44 100644 --- a/src/main/scala/radiance/tile/RadianceTile.scala +++ b/src/main/scala/radiance/tile/RadianceTile.scala @@ -193,7 +193,6 @@ class RadianceTile private ( } val imemTagWidth = UUID_WIDTH + NW_WIDTH - // val LSUQ_SIZE = p(SIMTCoreKey).get.nSrcIds require(numWarps >= numLsuLanes, s"Vortex core requires numWarps (${numWarps}) >= numLsuLanes (${numLsuLanes})") val LSUQ_SIZE = 8 * (numCoreLanes / numLsuLanes) From 358bf18b6dde7a2c9eb685f575b50234011fa4bf Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Tue, 7 May 2024 18:38:25 -0700 Subject: [PATCH 4/4] Bump vortex with merge fix --- src/main/resources/vsrc/vortex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/resources/vsrc/vortex b/src/main/resources/vsrc/vortex index 4aad161..be748b1 160000 --- a/src/main/resources/vsrc/vortex +++ b/src/main/resources/vsrc/vortex @@ -1 +1 @@ -Subproject commit 4aad161739773581a1df4037478e23a186d23cf2 +Subproject commit be748b109a6b468a1d59c39f0008d08a3e4076b4