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Remove unclear size width requirement in tl adapter

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This commit is contained in:
Hansung Kim
2023-11-27 16:42:07 -08:00
parent dafacf9873
commit 8ed82e8261
1 changed files with 1 additions and 2 deletions
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3
src/main/scala/tile/VortexTile.scala
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@@ -286,6 +286,7 @@ class VortexTile private (
// coalToVxCacheNode is a bad naming, it really means up steam of vxBank in whihc it takes input // coalToVxCacheNode is a bad naming, it really means up steam of vxBank in whihc it takes input
// imemNodes.foreach { l1cache.icache_bank.coalToVxCacheNode := TLWidthWidget(4) := _ } // imemNodes.foreach { l1cache.icache_bank.coalToVxCacheNode := TLWidthWidget(4) := _ }
imemNodes.foreach { l1cache.coresideNode := TLWidthWidget(4) := _ } imemNodes.foreach { l1cache.coresideNode := TLWidthWidget(4) := _ }
// dmemNodes go through coalescerNode
l1cache.coresideNode :=* coalescerNode l1cache.coresideNode :=* coalescerNode
l1cache.masterNode l1cache.masterNode
} }
@@ -587,8 +588,6 @@ class VortexTLAdapter(
io.outReq.bits.size := io.inReq.bits.size io.outReq.bits.size := io.inReq.bits.size
io.outReq.bits.source := io.inReq.bits.source io.outReq.bits.source := io.inReq.bits.source
io.outReq.bits.address := io.inReq.bits.address io.outReq.bits.address := io.inReq.bits.address
// this is just to double-check TLWidthWidget is in place
require(io.inReq.bits.size.getWidth == bundle.params.sizeBits)
// Get requires contiguous mask; only copy core's potentially-partial mask // Get requires contiguous mask; only copy core's potentially-partial mask
// when writing // when writing
io.outReq.bits.mask := Mux(edge.hasData(io.outReq.bits), io.outReq.bits.mask := Mux(edge.hasData(io.outReq.bits),