integrate vortex as tile
This commit is contained in:
Richard Yan
217
src/main/scala/tile/VortexTile.scala
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217
src/main/scala/tile/VortexTile.scala
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// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package tile
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import chisel3._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.rocket._
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import freechips.rocketchip.subsystem.TileCrossingParamsLike
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import freechips.rocketchip.util._
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import freechips.rocketchip.prci.ClockSinkParameters
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import freechips.rocketchip.tile._
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import rocket.Vortex
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import scala.collection.mutable.ListBuffer
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case class RocketTileBoundaryBufferParams(force: Boolean = false)
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case class VortexTileParams(
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core: RocketCoreParams = RocketCoreParams(),
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icache: Option[ICacheParams] = Some(ICacheParams(
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nSets = 64,
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nWays = 4,
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rowBits = 128,
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nTLBSets = 1,
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nTLBWays = 32,
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nTLBBasePageSectors = 4,
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nTLBSuperpages = 4,
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cacheIdBits = 0,
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blockBytes = 64,
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latency = 2,
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fetchBytes = 4
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)),
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dcache: Option[DCacheParams] = Some(DCacheParams(
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// TODO
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)),
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btb: Option[BTBParams] = None, // Some(BTBParams()),
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dataScratchpadBytes: Int = 0,
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name: Option[String] = Some("vortex_tile"),
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hartId: Int = 0,
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beuAddr: Option[BigInt] = None,
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blockerCtrlAddr: Option[BigInt] = None,
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clockSinkParams: ClockSinkParameters = ClockSinkParameters(),
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boundaryBuffers: Option[RocketTileBoundaryBufferParams] = None
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) extends InstantiableTileParams[VortexTile] {
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require(icache.isDefined)
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require(dcache.isDefined)
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def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): VortexTile = {
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new VortexTile(this, crossing, lookup)
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}
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}
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class VortexTile private(
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val vortexParams: VortexTileParams,
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crossing: ClockCrossingType,
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lookup: LookupByHartIdImpl,
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q: Parameters)
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extends BaseTile(vortexParams, crossing, lookup, q)
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with SinksExternalInterrupts
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with SourcesExternalNotifications
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{
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// Private constructor ensures altered LazyModule.p is used implicitly
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def this(params: VortexTileParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
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this(params, crossing.crossingType, lookup, p)
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val intOutwardNode = IntIdentityNode()
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val slaveNode = TLIdentityNode()
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val masterNode = visibilityNode
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// val dmemDevice = new SimpleDevice("dtim", Seq("sifive,dtim0"))
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/*val dmemNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
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Seq(TLSlaveParameters.v1(
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address = AddressSet.misaligned(tileParams.dcache.get.scratch.getOrElse(0),
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tileParams.dcache.get.nSets * tileParams.dcache.get.blockBytes),
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resources = dmemDevice.reg("mem"),
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regionType = RegionType.IDEMPOTENT,
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executable = true,
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supportsArithmetic = /*if (usingAtomics) TransferSizes(4, coreDataBytes) else*/ TransferSizes.none,
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supportsLogical = /*if (usingAtomics) TransferSizes(4, coreDataBytes) else*/ TransferSizes.none,
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supportsPutPartial = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
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supportsPutFull = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
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supportsGet = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
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fifoId = Some(0))), // requests handled in FIFO order
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beatBytes = lazyCoreParamsView.coreDataBytes,
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minLatency = 1)))*/
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val imemNode = TLClientNode(Seq(TLMasterPortParameters.v1(
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clients = Seq(TLMasterParameters.v1(
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sourceId = IdRange(0, 1 << 8), // TODO magic number
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name = s"Vortex Core I-Mem"
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))
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)))
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val dmemNode = TLClientNode(Seq(TLMasterPortParameters.v1(
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clients = Seq(TLMasterParameters.v1(
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sourceId = IdRange(0, 1 << 8), // TODO magic number
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name = s"Vortex Core D-Mem"
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))
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)))
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tlMasterXbar.node := imemNode
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tlMasterXbar.node := dmemNode
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val bus_error_unit = vortexParams.beuAddr map { a =>
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val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a)))
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intOutwardNode := beu.intNode
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connectTLSlave(beu.node, xBytes)
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beu
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}
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val tile_master_blocker =
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tileParams.blockerCtrlAddr
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.map(BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true))
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.map(bp => LazyModule(new BasicBusBlocker(bp)))
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tile_master_blocker.foreach(lm => connectTLSlave(lm.controlNode, xBytes))
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// TODO: this doesn't block other masters, e.g. RoCCs
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tlOtherMastersNode := tile_master_blocker.map { _.node := tlMasterXbar.node } getOrElse { tlMasterXbar.node }
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masterNode :=* tlOtherMastersNode
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DisableMonitors { implicit p => tlSlaveXbar.node :*= slaveNode }
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val dtimProperty = Nil //Seq(dmemDevice.asProperty).flatMap(p => Map("sifive,dtim" -> p))
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val itimProperty = Nil //frontend.icache.itimProperty.toSeq.flatMap(p => Map("sifive,itim" -> p))
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val beuProperty = bus_error_unit.map(d => Map(
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"sifive,buserror" -> d.device.asProperty)).getOrElse(Nil)
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val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("sifive,vortex0", "riscv")) {
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override def parent = Some(ResourceAnchors.cpus)
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override def describe(resources: ResourceBindings): Description = {
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val Description(name, mapping) = super.describe(resources)
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Description(name, mapping ++ cpuProperties ++ nextLevelCacheProperty
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++ tileProperties ++ dtimProperty ++ itimProperty ++ beuProperty)
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}
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}
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ResourceBinding {
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Resource(cpuDevice, "reg").bind(ResourceAddress(staticIdForMetadataUseOnly))
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}
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override lazy val module = new VortexTileModuleImp(this)
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override def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (vortexParams.boundaryBuffers, crossing) match {
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case (Some(RocketTileBoundaryBufferParams(true )), _) => TLBuffer()
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case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1))
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case _ => TLBuffer(BufferParams.none)
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}
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override def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (vortexParams.boundaryBuffers, crossing) match {
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case (Some(RocketTileBoundaryBufferParams(true )), _) => TLBuffer()
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case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none)
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case _ => TLBuffer(BufferParams.none)
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}
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}
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class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
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Annotated.params(this, outer.vortexParams)
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val core = Module(new Vortex(outer)(outer.p))
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core.io.clock := clock
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core.io.reset := reset
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// reset vector is connected in the Frontend to s2_pc
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core.io.reset_vector := DontCare
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// Report when the tile has ceased to retire instructions; for now the only cause is clock gating
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outer.reportCease(outer.vortexParams.core.clockGate.option(
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core.io.cease))
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outer.reportWFI(Some(core.io.wfi))
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outer.decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
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outer.bus_error_unit.foreach { beu =>
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core.io.interrupts.buserror.get := beu.module.io.interrupt
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}
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core.io.interrupts.nmi.foreach { nmi => nmi := outer.nmiSinkNode.bundle }
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// Pass through various external constants and reports that were bundle-bridged into the tile
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// outer.traceSourceNode.bundle <> core.io.trace
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core.io.traceStall := outer.traceAuxSinkNode.bundle.stall
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// outer.bpwatchSourceNode.bundle <> core.io.bpwatch
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core.io.hartid := outer.hartIdSinkNode.bundle
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require(core.io.hartid.getWidth >= outer.hartIdSinkNode.bundle.getWidth,
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s"core hartid wire (${core.io.hartid.getWidth}b) truncates external hartid wire (${outer.hartIdSinkNode.bundle.getWidth}b)")
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val (i_tl_out, _) = outer.imemNode.out.head
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val (d_tl_out, _) = outer.dmemNode.out.head
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core.io.imem.a <> i_tl_out.a
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core.io.imem.d <> i_tl_out.d
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core.io.dmem.a <> d_tl_out.a
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core.io.dmem.d <> d_tl_out.d
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core.io.fpu := DontCare
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// TODO eliminate this redundancy
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// val h = dcachePorts.size
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//val c = core.dcacheArbPorts
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// val o = outer.nDCachePorts
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// require(h == c, s"port list size was $h, core expected $c")
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// require(h == o, s"port list size was $h, outer counted $o")
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// TODO figure out how to move the below into their respective mix-ins
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// dcacheArb.io.requestor <> dcachePorts.toSeq
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}
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trait HasFpuOpt { this: RocketTileModuleImp =>
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val fpuOpt = outer.tileParams.core.fpu.map(params => Module(new FPU(params)(outer.p)))
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}
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