diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala
index 9885a16..49f501c 100644
--- a/src/main/scala/tilelink/Coalescing.scala
+++ b/src/main/scala/tilelink/Coalescing.scala
@@ -1132,14 +1132,6 @@ class Uncoalescer(
   (foundRow.lanes zip io.respQueueIO).zipWithIndex.foreach { case ((foundLane, enqIOs), lane) =>
     foundLane.reqs.zipWithIndex.foreach { case (foundReq, depth) =>
       val enqIO = enqIOs(depth)
-
-      // TODO: rather than crashing, deassert tlOut.d.ready to stall downtream
-      // cache.  This should ideally not happen though (and hasn't happened yet
-      // in testing.)
-      assert(
-        enqIO.ready,
-        s"respQueue: enq port for ${depth}-th uncoalesced response is blocked for lane ${lane}"
-      )
       // spatial-only coalescing: only looking at 0th srcId entry
       enqIO.valid := false.B
       enqIO.bits := DontCare