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Move VortexBundleA/D to Core; resolve TODOs

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This commit is contained in:
Hansung Kim
2023-10-16 17:54:12 -07:00
parent eb9772b750
commit 8ab0529354
2 changed files with 19 additions and 25 deletions
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18
src/main/scala/rocket/VortexCore.scala
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@@ -8,7 +8,23 @@ import chisel3.util._
import chisel3.experimental._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile._
import tile.{VortexTile, VortexBundleA, VortexBundleD}
import tile.VortexTile
class VortexBundleA extends Bundle {
val opcode = UInt(3.W) // FIXME: hardcoded
val size = UInt(4.W) // FIXME: hardcoded
val source = UInt(10.W) // FIXME: hardcoded
val address = UInt(32.W) // FIXME: hardcoded
val mask = UInt(4.W) // FIXME: hardcoded
val data = UInt(32.W) // FIXME: hardcoded
}
class VortexBundleD extends Bundle {
val opcode = UInt(3.W) // FIXME: hardcoded
val size = UInt(4.W) // FIXME: hardcoded
val source = UInt(10.W) // FIXME: hardcoded
val data = UInt(32.W) // FIXME: hardcoded
}
class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle {
val clock = Input(Clock())