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Replace hardcoded trace widths with proper params

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This commit is contained in:
Hansung Kim
2023-04-21 18:20:16 -07:00
parent bbe62a8583
commit 8a7e6f1391
3 changed files with 35 additions and 20 deletions
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12
src/main/resources/vsrc/SimMemTrace.v
View File

@@ -1,7 +1,7 @@
// FIXME hardcoded
`define DATA_WIDTH 64
`define MAX_NUM_LANES 32
`define LOGSIZE_WIDTH 32
`define LOGSIZE_WIDTH 8
import "DPI-C" function void memtrace_init(
input string filename
@@ -41,7 +41,7 @@ module SimMemTrace #(parameter FILENAME = "undefined", NUM_LANES = 4) (
longint __in_address [NUM_LANES-1:0];
bit __in_is_store [NUM_LANES-1:0];
int __in_size [NUM_LANES-1:0];
reg [`LOGSIZE_WIDTH-1:0] __in_size [NUM_LANES-1:0];
longint __in_data [NUM_LANES-1:0];
bit __in_finished;
@@ -57,10 +57,10 @@ module SimMemTrace #(parameter FILENAME = "undefined", NUM_LANES = 4) (
reg [NUM_LANES-1:0] __in_valid_reg;
reg [`DATA_WIDTH-1:0] __in_address_reg [NUM_LANES-1:0];
reg [NUM_LANES-1:0] __in_is_store_reg;
int __in_size_reg [NUM_LANES-1:0];
reg [`DATA_WIDTH-1:0] __in_data_reg [NUM_LANES-1:0];
reg __in_finished_reg;
reg [NUM_LANES-1:0] __in_is_store_reg;
reg [`LOGSIZE_WIDTH-1:0] __in_size_reg [NUM_LANES-1:0];
reg [`DATA_WIDTH-1:0] __in_data_reg [NUM_LANES-1:0];
reg __in_finished_reg;
genvar g;

2
src/main/resources/vsrc/SimMemTraceLogger.v
View File

@@ -2,7 +2,7 @@
`define DATA_WIDTH 64
`define MAX_NUM_LANES 32
`define SOURCEID_WIDTH 32
`define LOGSIZE_WIDTH 32
`define LOGSIZE_WIDTH 8
import "DPI-C" function int memtracelogger_init(
input bit is_response,

41
src/main/scala/tilelink/Coalescing.scala
View File

@@ -282,7 +282,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, numLanes: Int) extends LazyModule
r.valid := false.B
r.source := i.U // FIXME bogus
r.offset := 1.U
r.size := 2.U
r.size := 2.U // FIXME hardcoded
}
}
newEntry.lanes(0).reqs(0).valid := true.B
@@ -669,7 +669,8 @@ trait HasTraceLine {
val data: UInt
}
// used for both request and response. response had address set to 0
// Used for both request and response. Response had address set to 0
// NOTE: these widths have to agree with what's hardcoded in Verilog.
class TraceLine extends Bundle with HasTraceLine {
val valid = Bool()
val source = UInt(32.W)
@@ -693,14 +694,17 @@ class MemTraceDriverImp(outer: MemTraceDriver, numLanes: Int, traceFile: String)
// back to each lane's.
val laneReqs = Wire(Vec(numLanes, new TraceLine))
val addrW = laneReqs(0).address.getWidth
val sizeW = laneReqs(0).size.getWidth
val dataW = laneReqs(0).data.getWidth
laneReqs.zipWithIndex.foreach { case (req, i) =>
req.valid := sim.io.trace_read.valid(i)
// TODO: don't take source id from the original trace for now
// TODO: driver trace doesn't contain source id
req.source := 0.U
req.address := sim.io.trace_read.address(64 * i + 63, 64 * i)
req.address := sim.io.trace_read.address(addrW * (i + 1) - 1, addrW * i)
req.is_store := sim.io.trace_read.is_store(i)
req.size := sim.io.trace_read.size(32 * i + 31, 32 * i)
req.data := sim.io.trace_read.data(64 * i + 63, 64 * i)
req.size := sim.io.trace_read.size(sizeW * (i + 1) - 1, sizeW * i)
req.data := sim.io.trace_read.data(dataW * (i + 1) - 1, dataW * i)
}
// To prevent collision of sourceId with a current in-flight message,
@@ -781,6 +785,11 @@ class SimMemTrace(filename: String, numLanes: Int)
Map("FILENAME" -> filename, "NUM_LANES" -> numLanes)
)
with HasBlackBoxResource {
val traceLineT = new TraceLine
val addrW = traceLineT.address.getWidth
val sizeW = traceLineT.size.getWidth
val dataW = traceLineT.data.getWidth
val io = IO(new Bundle {
val clock = Input(Clock())
val reset = Input(Bool())
@@ -793,10 +802,10 @@ class SimMemTrace(filename: String, numLanes: Int)
// Chisel can't interface with Verilog 2D port, so flatten all lanes into
// single wide 1D array.
// TODO: assumes 64-bit address.
val address = Output(UInt((64 * numLanes).W))
val address = Output(UInt((addrW * numLanes).W))
val is_store = Output(UInt(numLanes.W))
val size = Output(UInt((32 * numLanes).W))
val data = Output(UInt((64 * numLanes).W))
val size = Output(UInt((sizeW * numLanes).W))
val data = Output(UInt((dataW * numLanes).W))
val finished = Output(Bool())
}
})
@@ -1019,20 +1028,26 @@ class SimMemTraceLogger(isResponse: Boolean, filename: String, numLanes: Int)
)
)
with HasBlackBoxResource {
val traceLineT = new TraceLine
val sourceW = traceLineT.source.getWidth
val addrW = traceLineT.address.getWidth
val sizeW = traceLineT.size.getWidth
val dataW = traceLineT.data.getWidth
val io = IO(new Bundle {
val clock = Input(Clock())
val reset = Input(Bool())
val trace_log = new Bundle with HasTraceLine {
val valid = Input(UInt(numLanes.W))
val source = Input(UInt((32 * numLanes).W))
val source = Input(UInt((sourceW * numLanes).W))
// Chisel can't interface with Verilog 2D port, so flatten all lanes into
// single wide 1D array.
// TODO: assumes 64-bit address.
val address = Input(UInt((64 * numLanes).W))
val address = Input(UInt((addrW * numLanes).W))
val is_store = Input(UInt(numLanes.W))
val size = Input(UInt((32 * numLanes).W))
val data = Input(UInt((64 * numLanes).W))
val size = Input(UInt((sizeW * numLanes).W))
val data = Input(UInt((dataW * numLanes).W))
val ready = Output(Bool())
}
})