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trait HasTraceReq

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This commit is contained in:
Hansung Kim
2023-04-17 16:51:37 -07:00
parent f60602fc34
commit 8978c2a812
3 changed files with 15 additions and 15 deletions
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6
src/main/resources/csrc/SimMemTrace.h
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@@ -30,13 +30,9 @@ class MemTraceWriter {
public: public:
MemTraceWriter(const std::string &filename); MemTraceWriter(const std::string &filename);
~MemTraceWriter(); ~MemTraceWriter();
// void parse(); void write_line_to_trace(const MemTraceLine line);
void write_trace_at(const MemTraceLine line);
// bool finished() const { return read_pos == trace.cend(); }
FILE *outfile; FILE *outfile;
// std::vector<MemTraceLine> trace;
// std::vector<MemTraceLine>::const_iterator read_pos;
}; };
extern "C" void memtrace_init(const char *filename); extern "C" void memtrace_init(const char *filename);

8
src/main/resources/csrc/SimMemTraceLogger.cc
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@@ -16,7 +16,7 @@ static std::unique_ptr<MemTraceWriter> logger;
MemTraceWriter::MemTraceWriter(const std::string &filename) { MemTraceWriter::MemTraceWriter(const std::string &filename) {
char cwd[4096]; char cwd[4096];
if (getcwd(cwd, sizeof(cwd))) { if (getcwd(cwd, sizeof(cwd))) {
printf("MemTraceLogger: current working dir: %s\n", cwd); printf("MemTraceWriter: current working dir: %s\n", cwd);
} }
outfile = fopen(filename.c_str(), "w"); outfile = fopen(filename.c_str(), "w");
@@ -30,9 +30,7 @@ MemTraceWriter::~MemTraceWriter() {
printf("MemTraceWriter destroyed\n"); printf("MemTraceWriter destroyed\n");
} }
void MemTraceWriter::write_trace_at(const MemTraceLine line) { void MemTraceWriter::write_line_to_trace(const MemTraceLine line) {
printf("tick(): cycle=%ld\n", line.cycle);
fprintf(outfile, "%ld %s %d %d 0x%lx 0x%lx %u\n", line.cycle, fprintf(outfile, "%ld %s %d %d 0x%lx 0x%lx %u\n", line.cycle,
(line.is_store ? "STORE" : "LOAD"), line.core_id, line.lane_id, (line.is_store ? "STORE" : "LOAD"), line.core_id, line.lane_id,
line.address, line.data, (1u << line.log_data_size)); line.address, line.data, (1u << line.log_data_size));
@@ -91,5 +89,5 @@ extern "C" void memtracelogger_log(unsigned char trace_log_valid,
.data = trace_log_data, .data = trace_log_data,
.log_data_size = trace_log_size}; .log_data_size = trace_log_size};
logger->write_trace_at(line); logger->write_line_to_trace(line);
} }

16
src/main/scala/tilelink/Coalescing.scala
View File

@@ -607,9 +607,15 @@ class MemTraceDriver(numLanes: Int = 4, filename: String = "vecadd.core1.thread4
lazy val module = new MemTraceDriverImp(this, numLanes, filename) lazy val module = new MemTraceDriverImp(this, numLanes, filename)
} }
// TODO: this is replicated in sim.io.trace_read and sim.io.trace_log; make it trait HasTraceReq {
// into a trait val valid: UInt
class TraceReq extends Bundle { val address: UInt
val is_store: UInt
val size: UInt
val data: UInt
}
class TraceReq extends Bundle with HasTraceReq {
val valid = Bool() val valid = Bool()
val address = UInt(64.W) val address = UInt(64.W)
val is_store = Bool() val is_store = Bool()
@@ -722,7 +728,7 @@ class SimMemTrace(filename: String, numLanes: Int)
// These names have to match declarations in the Verilog code, eg. // These names have to match declarations in the Verilog code, eg.
// trace_read_address. // trace_read_address.
val trace_read = new Bundle { val trace_read = new Bundle with HasTraceReq {
val ready = Input(Bool()) val ready = Input(Bool())
val valid = Output(UInt(numLanes.W)) val valid = Output(UInt(numLanes.W))
// Chisel can't interface with Verilog 2D port, so flatten all lanes into // Chisel can't interface with Verilog 2D port, so flatten all lanes into
@@ -867,7 +873,7 @@ class SimMemTraceLogger(filename: String, numLanes: Int)
val clock = Input(Clock()) val clock = Input(Clock())
val reset = Input(Bool()) val reset = Input(Bool())
val trace_log = new Bundle { val trace_log = new Bundle with HasTraceReq {
val valid = Input(UInt(numLanes.W)) val valid = Input(UInt(numLanes.W))
// Chisel can't interface with Verilog 2D port, so flatten all lanes into // Chisel can't interface with Verilog 2D port, so flatten all lanes into
// single wide 1D array. // single wide 1D array.