trait HasTraceReq

src/main/resources/csrc/SimMemTrace.h

@@ -30,13 +30,9 @@ class MemTraceWriter {
 public:
   MemTraceWriter(const std::string &filename);
   ~MemTraceWriter();
-  // void parse();
-  void write_trace_at(const MemTraceLine line);
-  // bool finished() const { return read_pos == trace.cend(); }
+  void write_line_to_trace(const MemTraceLine line);
 
   FILE *outfile;
-  // std::vector<MemTraceLine> trace;
-  // std::vector<MemTraceLine>::const_iterator read_pos;
 };
 
 extern "C" void memtrace_init(const char *filename);

src/main/resources/csrc/SimMemTraceLogger.cc

@@ -16,7 +16,7 @@ static std::unique_ptr<MemTraceWriter> logger;
 MemTraceWriter::MemTraceWriter(const std::string &filename) {
   char cwd[4096];
   if (getcwd(cwd, sizeof(cwd))) {
-    printf("MemTraceLogger: current working dir: %s\n", cwd);
+    printf("MemTraceWriter: current working dir: %s\n", cwd);
   }
 
   outfile = fopen(filename.c_str(), "w");
@@ -30,9 +30,7 @@ MemTraceWriter::~MemTraceWriter() {
   printf("MemTraceWriter destroyed\n");
 }
 
-void MemTraceWriter::write_trace_at(const MemTraceLine line) {
-  printf("tick(): cycle=%ld\n", line.cycle);
-
+void MemTraceWriter::write_line_to_trace(const MemTraceLine line) {
   fprintf(outfile, "%ld %s %d %d 0x%lx 0x%lx %u\n", line.cycle,
           (line.is_store ? "STORE" : "LOAD"), line.core_id, line.lane_id,
           line.address, line.data, (1u << line.log_data_size));
@@ -91,5 +89,5 @@ extern "C" void memtracelogger_log(unsigned char trace_log_valid,
                     .data = trace_log_data,
                     .log_data_size = trace_log_size};
 
-  logger->write_trace_at(line);
+  logger->write_line_to_trace(line);
 }

src/main/scala/tilelink/Coalescing.scala

@@ -607,9 +607,15 @@ class MemTraceDriver(numLanes: Int = 4, filename: String = "vecadd.core1.thread4
   lazy val module = new MemTraceDriverImp(this, numLanes, filename)
 }
 
-// TODO: this is replicated in sim.io.trace_read and sim.io.trace_log; make it
-// into a trait
-class TraceReq extends Bundle {
+trait HasTraceReq {
+  val valid: UInt
+  val address: UInt
+  val is_store: UInt
+  val size: UInt
+  val data: UInt
+}
+
+class TraceReq extends Bundle with HasTraceReq {
   val valid = Bool()
   val address = UInt(64.W)
   val is_store = Bool()
@@ -722,7 +728,7 @@ class SimMemTrace(filename: String, numLanes: Int)
 
     // These names have to match declarations in the Verilog code, eg.
     // trace_read_address.
-    val trace_read = new Bundle {
+    val trace_read = new Bundle with HasTraceReq {
       val ready = Input(Bool())
       val valid = Output(UInt(numLanes.W))
       // Chisel can't interface with Verilog 2D port, so flatten all lanes into
@@ -867,7 +873,7 @@ class SimMemTraceLogger(filename: String, numLanes: Int)
     val clock = Input(Clock())
     val reset = Input(Bool())
 
-    val trace_log = new Bundle {
+    val trace_log = new Bundle with HasTraceReq {
       val valid = Input(UInt(numLanes.W))
       // Chisel can't interface with Verilog 2D port, so flatten all lanes into
       // single wide 1D array.