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Fix CanHaveMemtraceCore not setting numLane

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This commit is contained in:
Hansung Kim
2023-05-09 19:02:03 -07:00
parent 2ade624343
commit 89398cdc3d
1 changed files with 4 additions and 1 deletions
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5
src/main/scala/tilelink/TracerSystemMem.scala
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@@ -10,7 +10,10 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
implicit val p: Parameters implicit val p: Parameters
p(MemtraceCoreKey).map { param => p(MemtraceCoreKey).map { param =>
val tracer = LazyModule(new MemTraceDriver(defaultConfig, param.tracefilename)(p)) // Safe to use get as WithMemtraceCore requires WithNLanes to be defined
val simtParam = p(SIMTCoreKey).get
val config = defaultConfig.copy(numLanes = simtParam.nLanes)
val tracer = LazyModule(new MemTraceDriver(config, param.tracefilename)(p))
// Must use :=* to ensure the N edges from Tracer doesn't get merged into 1 // Must use :=* to ensure the N edges from Tracer doesn't get merged into 1
// when connecting to SBus // when connecting to SBus
println(s"============ MemTraceDriver instantiated [filename=${param.tracefilename}]") println(s"============ MemTraceDriver instantiated [filename=${param.tracefilename}]")