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Force numBanks = 1 for icache

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Given that the number of imem port is 1 and imem access has good spatial
locality, force single bank config for icache.
This commit is contained in:
Hansung Kim
2024-03-07 17:18:59 -08:00
parent 396fddf437
commit 8680c64e5b
1 changed files with 2 additions and 1 deletions
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src/main/scala/radiance/tile/RadianceTile.scala
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@@ -303,12 +303,13 @@ class RadianceTile private (
// Conditionally instantiate L1 cache // Conditionally instantiate L1 cache
val (icacheNode, dcacheNode): (TLNode, TLNode) = p(VortexL1Key) match { val (icacheNode, dcacheNode): (TLNode, TLNode) = p(VortexL1Key) match {
case Some(vortexL1Config) => { case Some(vortexL1Config) => {
println("VortexL1Cache instantiated")
// require( // require(
// p(CoalescerKey).isDefined, // p(CoalescerKey).isDefined,
// "Vortex L1 configuration currently only works when coalescer is also enabled." // "Vortex L1 configuration currently only works when coalescer is also enabled."
// ) // )
val icache = LazyModule(new VortexL1Cache(vortexL1Config)) val icache = LazyModule(new VortexL1Cache(vortexL1Config.copy(numBanks = 1)))
val dcache = LazyModule(new VortexL1Cache(vortexL1Config)) val dcache = LazyModule(new VortexL1Cache(vortexL1Config))
// imemNodes.foreach { icache.coresideNode := TLWidthWidget(4) := _ } // imemNodes.foreach { icache.coresideNode := TLWidthWidget(4) := _ }
assert(imemNodes.length == 1) // FIXME assert(imemNodes.length == 1) // FIXME