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Add assertion on numWarps >= numLsuLanes

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This commit is contained in:
Hansung Kim
2024-05-03 14:22:23 -07:00
parent f698768b39
commit 8148cc361c
1 changed files with 7 additions and 3 deletions
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10
src/main/scala/radiance/tile/RadianceTile.scala
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@@ -193,9 +193,13 @@ class RadianceTile private (
} }
val imemTagWidth = UUID_WIDTH + NW_WIDTH val imemTagWidth = UUID_WIDTH + NW_WIDTH
// val LSUQ_SIZE = 4 * numWarps * (numCoreLanes / numLsuLanes) // val LSUQ_SIZE = p(SIMTCoreKey).get.nSrcIds
// assert(LSUQ_SIZE == p(SIMTCoreKey).get.nSrcIds) require(numWarps >= numLsuLanes,
val LSUQ_SIZE = p(SIMTCoreKey).get.nSrcIds s"Vortex core requires numWarps (${numWarps}) >= numLsuLanes (${numLsuLanes})")
val LSUQ_SIZE = 8 * (numCoreLanes / numLsuLanes)
require(LSUQ_SIZE == p(SIMTCoreKey).get.nSrcIds,
s"LSUQ_SIZE (${LSUQ_SIZE}) != nSrcIds (${p(SIMTCoreKey).get.nSrcIds})"
+ " which can result in TileLink srcId underutilization")
val LSUQ_TAG_BITS = log2Ceil(LSUQ_SIZE) + 1 /*DCACHE_BATCH_SEL_BITS*/ val LSUQ_TAG_BITS = log2Ceil(LSUQ_SIZE) + 1 /*DCACHE_BATCH_SEL_BITS*/
val dmemTagWidth = UUID_WIDTH + LSUQ_TAG_BITS val dmemTagWidth = UUID_WIDTH + LSUQ_TAG_BITS
// dmem and smem shares the same tag width, DCACHE_NOSM_TAG_WIDTH // dmem and smem shares the same tag width, DCACHE_NOSM_TAG_WIDTH