From 8148cc361c5e79dbe2a4d82c7212a4d6f6f8b3b1 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Fri, 3 May 2024 14:22:23 -0700 Subject: [PATCH] Add assertion on numWarps >= numLsuLanes --- src/main/scala/radiance/tile/RadianceTile.scala | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/main/scala/radiance/tile/RadianceTile.scala b/src/main/scala/radiance/tile/RadianceTile.scala index 502371e..6b0e842 100644 --- a/src/main/scala/radiance/tile/RadianceTile.scala +++ b/src/main/scala/radiance/tile/RadianceTile.scala @@ -193,9 +193,13 @@ class RadianceTile private ( } val imemTagWidth = UUID_WIDTH + NW_WIDTH - // val LSUQ_SIZE = 4 * numWarps * (numCoreLanes / numLsuLanes) - // assert(LSUQ_SIZE == p(SIMTCoreKey).get.nSrcIds) - val LSUQ_SIZE = p(SIMTCoreKey).get.nSrcIds + // val LSUQ_SIZE = p(SIMTCoreKey).get.nSrcIds + require(numWarps >= numLsuLanes, + s"Vortex core requires numWarps (${numWarps}) >= numLsuLanes (${numLsuLanes})") + val LSUQ_SIZE = 8 * (numCoreLanes / numLsuLanes) + require(LSUQ_SIZE == p(SIMTCoreKey).get.nSrcIds, + s"LSUQ_SIZE (${LSUQ_SIZE}) != nSrcIds (${p(SIMTCoreKey).get.nSrcIds})" + + " which can result in TileLink srcId underutilization") val LSUQ_TAG_BITS = log2Ceil(LSUQ_SIZE) + 1 /*DCACHE_BATCH_SEL_BITS*/ val dmemTagWidth = UUID_WIDTH + LSUQ_TAG_BITS // dmem and smem shares the same tag width, DCACHE_NOSM_TAG_WIDTH