diff --git a/src/main/resources/csrc/SimMemTrace.cc b/src/main/resources/csrc/SimMemTrace.cc
new file mode 100644
index 0000000..61096cd
--- /dev/null
+++ b/src/main/resources/csrc/SimMemTrace.cc
@@ -0,0 +1,22 @@
+#include <vpi_user.h>
+#include <svdpi.h>
+
+#include <stdio.h>
+#include <string.h>
+
+extern "C" void memtrace_init(
+        const char *filename)
+{
+    printf("memtrace_init: filename=[%s]\n", filename);
+}
+
+extern "C" void memtrace_tick(
+        unsigned char *trace_read_valid,
+        unsigned char trace_read_ready,
+        char *trace_read_bits)
+{
+    printf("tick!\n");
+    *trace_read_valid = 1;
+    *trace_read_bits = 42;
+    return;
+}
diff --git a/src/main/resources/vsrc/SimMemTrace.v b/src/main/resources/vsrc/SimMemTrace.v
new file mode 100644
index 0000000..99b8b1f
--- /dev/null
+++ b/src/main/resources/vsrc/SimMemTrace.v
@@ -0,0 +1,58 @@
+`define DATA_WIDTH 8
+
+import "DPI-C" function void memtrace_init(
+    input  string  filename
+);
+
+import "DPI-C" function void memtrace_tick
+(
+    output bit     trace_read_valid,
+    input  bit     trace_read_ready,
+    output byte    trace_read_bits
+);
+
+module SimMemTrace  (
+    input              clock,
+    input              reset,
+
+    output                   trace_read_valid,
+    input                    trace_read_ready,
+    output [`DATA_WIDTH-1:0] trace_read_bits
+);
+
+    bit __in_valid;
+    byte __in_bits;
+    string __uartlog;
+    int __uartno;
+
+    initial begin
+        $value$plusargs("uartlog=%s", __uartlog);
+        memtrace_init(__uartlog);
+    end
+
+    reg __in_valid_reg;
+    reg [`DATA_WIDTH-1:0] __in_bits_reg;
+
+    assign trace_read_valid  = __in_valid_reg;
+    assign trace_read_bits   = __in_bits_reg;
+
+    // Evaluate the signals on the positive edge
+    always @(posedge clock) begin
+        if (reset) begin
+            __in_valid = 0;
+
+            __in_valid_reg <= 0;
+            __in_bits_reg <= 0;
+        end else begin
+            memtrace_tick(
+                __in_valid,
+                trace_read_ready,
+                __in_bits
+            );
+
+            __in_valid_reg  <= __in_valid;
+            __in_bits_reg   <= __in_bits;
+        end
+    end
+
+endmodule
diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala
index dccc7c2..69d6c59 100644
--- a/src/main/scala/tilelink/Coalescing.scala
+++ b/src/main/scala/tilelink/Coalescing.scala
@@ -3,12 +3,54 @@
 package freechips.rocketchip.tilelink
 
 import chisel3._
+import chisel3.util._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.unittest._
 
-class CoalescingUnitTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
-  val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module)
-  dut.io.start := io.start
-  io.finished := true.B
+class CoalescingUnit(txns: Int = 5000)(implicit p: Parameters) extends LazyModule {
+  val fuzz = LazyModule(new TLFuzzer(txns))
+  val model = LazyModule(new TLRAMModel("Xbar"))
+  val xbar = LazyModule(new TLXbar)
+
+  xbar.node := TLDelayer(0.1) := model.node := fuzz.node
+  (0 until 1) foreach { n =>
+    val ram  = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
+    ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
+  }
+
+  lazy val module = new Impl
+  class Impl extends LazyModuleImp(this) {
+    // io.finished := fuzz.module.io.finished
+  }
+}
+
+class SimMemTrace()(implicit p: Parameters) extends BlackBox
+with HasBlackBoxResource {
+  val io = IO(new Bundle {
+    val clock = Input(Clock())
+    val reset = Input(Bool())
+
+    val trace_read = new Bundle {
+      val ready = Input(Bool())
+      val valid = Output(Bool())
+      val bits = Output(UInt(8.W))
+    }
+  })
+
+  addResource("/vsrc/SimMemTrace.v")
+  addResource("/csrc/SimMemTrace.cc")
+}
+
+class CoalescingUnitTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters)
+extends UnitTest(timeout) {
+  val dut = Module(LazyModule(new CoalescingUnit(txns)).module)
+  // dut.io.start := io.start
+
+  val sim = Module(new SimMemTrace)
+  sim.io.clock := clock
+  sim.io.reset := reset.asBool
+  sim.io.trace_read.ready := true.B
+
+  io.finished := sim.io.trace_read.valid
 }