From 7cfa994890a7e7a4cf1c614b28110dac4c0bd4ff Mon Sep 17 00:00:00 2001 From: Richard Yan Date: Mon, 5 Feb 2024 12:01:49 -0800 Subject: [PATCH] bug fix for address rewriter --- src/main/scala/radiance/memory/AddressRewriterNode.scala | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/main/scala/radiance/memory/AddressRewriterNode.scala b/src/main/scala/radiance/memory/AddressRewriterNode.scala index 82723bb..c0bae8c 100644 --- a/src/main/scala/radiance/memory/AddressRewriterNode.scala +++ b/src/main/scala/radiance/memory/AddressRewriterNode.scala @@ -1,6 +1,7 @@ package radiance.memory import chisel3._ +import chisel3.experimental.SourceInfo import chisel3.util._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink.TLAdapterNode @@ -8,10 +9,10 @@ import org.chipsalliance.cde.config.Parameters class AddressRewriterNode(baseAddr: BigInt)(implicit p: Parameters) extends LazyModule { - require(isPow2(baseAddr), "base address must be a power of 2") + require(isPow2(baseAddr) || (baseAddr == 0), "base address must be a power of 2") val node = TLAdapterNode(clientFn = c => c, managerFn = m => m) - val module = new LazyModuleImp(this) { + lazy val module = new LazyModuleImp(this) { (node.in.map(_._1) zip node.out.map(_._1)).foreach { case (i, o) => o.a <> i.a o.a.bits.address := i.a.bits.address | baseAddr.U @@ -21,7 +22,7 @@ class AddressRewriterNode(baseAddr: BigInt)(implicit p: Parameters) extends Lazy } object AddressRewriterNode { - def apply(baseAddr: BigInt)(implicit p: Parameters): TLAdapterNode = { - new AddressRewriterNode(baseAddr).node + def apply(baseAddr: BigInt)(implicit p: Parameters, valName: ValName, sourceInfo: SourceInfo): TLAdapterNode = { + LazyModule(new AddressRewriterNode(baseAddr)).node } } \ No newline at end of file