multilane support, args.bin ROM, verilog sources cleanup and vortex bump

src/main/scala/rocket/VortexCore.scala

@@ -34,16 +34,16 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
   addResource("/vsrc/vortex/hw/rtl/VX_dispatch.sv")
   addResource("/vsrc/vortex/hw/rtl/VX_issue.sv")
   // addResource("/vsrc/vortex/hw/rtl/cache/VX_shared_mem.sv")
-  addResource("/vsrc/vortex/hw/rtl/cache/VX_core_rsp_merge.sv")
+  // addResource("/vsrc/vortex/hw/rtl/cache/VX_core_rsp_merge.sv")
-  addResource("/vsrc/vortex/hw/rtl/cache/VX_tag_access.sv")
+  // addResource("/vsrc/vortex/hw/rtl/cache/VX_tag_access.sv")
-  addResource("/vsrc/vortex/hw/rtl/cache/VX_core_req_bank_sel.sv")
+  // addResource("/vsrc/vortex/hw/rtl/cache/VX_core_req_bank_sel.sv")
-  addResource("/vsrc/vortex/hw/rtl/cache/VX_bank.sv")
+  // addResource("/vsrc/vortex/hw/rtl/cache/VX_bank.sv")
-  addResource("/vsrc/vortex/hw/rtl/cache/VX_cache.sv")
+  // addResource("/vsrc/vortex/hw/rtl/cache/VX_cache.sv")
-  addResource("/vsrc/vortex/hw/rtl/cache/VX_data_access.sv")
+  // addResource("/vsrc/vortex/hw/rtl/cache/VX_data_access.sv")
   addResource("/vsrc/vortex/hw/rtl/cache/VX_cache_define.vh")
-  addResource("/vsrc/vortex/hw/rtl/cache/VX_flush_ctrl.sv")
+  // addResource("/vsrc/vortex/hw/rtl/cache/VX_flush_ctrl.sv")
-  addResource("/vsrc/vortex/hw/rtl/cache/VX_nc_bypass.sv")
+  // addResource("/vsrc/vortex/hw/rtl/cache/VX_nc_bypass.sv")
-  addResource("/vsrc/vortex/hw/rtl/cache/VX_miss_resrv.sv")
+  // addResource("/vsrc/vortex/hw/rtl/cache/VX_miss_resrv.sv")
   addResource("/vsrc/vortex/hw/rtl/VX_warp_sched.sv")
   // addResource("/vsrc/vortex/hw/rtl/Vortex.sv")
   addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_sat.sv")
@@ -69,16 +69,16 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
   addResource("/vsrc/vortex/hw/rtl/VX_trace_instr.vh")
   addResource("/vsrc/vortex/hw/rtl/VX_gpu_types.vh")
   addResource("/vsrc/vortex/hw/rtl/VX_config.vh")
-  addResource("/vsrc/vortex/hw/rtl/libs/VX_mux.sv")
+  // unused addResource("/vsrc/vortex/hw/rtl/libs/VX_mux.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_lzc.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_fifo_queue.sv")
-  addResource("/vsrc/vortex/hw/rtl/libs/VX_scope.sv")
+  // unused addResource("/vsrc/vortex/hw/rtl/libs/VX_scope.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_scan.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_find_first.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_multiplier.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_bits_remove.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_pipe_register.sv")
-  addResource("/vsrc/vortex/hw/rtl/libs/VX_onehot_mux.sv")
+  // unused addResource("/vsrc/vortex/hw/rtl/libs/VX_onehot_mux.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_priority_encoder.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_reset_relay.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_popcount.sv")
@@ -89,17 +89,17 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
   addResource("/vsrc/vortex/hw/rtl/libs/VX_index_buffer.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_onehot_encoder.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_matrix_arbiter.sv")
-  addResource("/vsrc/vortex/hw/rtl/libs/VX_divider.sv")
+  // unused addResource("/vsrc/vortex/hw/rtl/libs/VX_divider.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_dp_ram.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_axi_adapter.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_elastic_buffer.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_rr_arbiter.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_stream_arbiter.sv")
-  addResource("/vsrc/vortex/hw/rtl/libs/VX_bypass_buffer.sv")
+  // unused addResource("/vsrc/vortex/hw/rtl/libs/VX_bypass_buffer.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_sp_ram.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_stream_demux.sv")
-  addResource("/vsrc/vortex/hw/rtl/libs/VX_pending_size.sv")
+  // addResource("/vsrc/vortex/hw/rtl/libs/VX_pending_size.sv")
-  addResource("/vsrc/vortex/hw/rtl/libs/VX_index_queue.sv")
+  // unused addResource("/vsrc/vortex/hw/rtl/libs/VX_index_queue.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_serial_div.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_fair_arbiter.sv")
   addResource("/vsrc/vortex/hw/rtl/VX_define.vh")
@@ -110,10 +110,10 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
   addResource("/vsrc/vortex/hw/rtl/VX_execute.sv")
   addResource("/vsrc/vortex/hw/rtl/VX_fetch.sv")
   addResource("/vsrc/vortex/hw/rtl/VX_alu_unit.sv")
-  addResource("/vsrc/vortex/hw/rtl/VX_mem_arb.sv")
+  // unused addResource("/vsrc/vortex/hw/rtl/VX_mem_arb.sv")
   addResource("/vsrc/vortex/hw/rtl/VX_platform.vh")
   addResource("/vsrc/vortex/hw/rtl/VX_commit.sv")
-  addResource("/vsrc/vortex/hw/rtl/VX_smem_arb.sv")
+  // unused addResource("/vsrc/vortex/hw/rtl/VX_smem_arb.sv")
   addResource("/vsrc/vortex/hw/rtl/VX_pipeline.sv")
   addResource("/vsrc/vortex/hw/rtl/VX_lsu_unit.sv")
   // addResource("/vsrc/vortex/hw/rtl/VX_mem_unit.sv")
@@ -206,14 +206,14 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
     val hartid = Input(UInt(hartIdLen.W))
     val reset_vector = Input(UInt(resetVectorLen.W))
     val interrupts = Input(new CoreInterrupts())
-    val imem = new Bundle {
+    val imem = Vec(1, new Bundle { // TODO: magic number
-      val a = tile.imemNode.out.head._1.a.cloneType
+      val a = tile.imemNodes.head.out.head._1.a.cloneType
-      val d = Flipped(tile.imemNode.out.head._1.d.cloneType)
+      val d = Flipped(tile.imemNodes.head.out.head._1.d.cloneType)
-    }
+    })
-    val dmem = new Bundle {
+    val dmem = Vec(4, new Bundle {
-      val a = tile.dmemNode.out.head._1.a.cloneType
+      val a = tile.dmemNodes.head.out.head._1.a.cloneType
-      val d = Flipped(tile.dmemNode.out.head._1.d.cloneType)
+      val d = Flipped(tile.dmemNodes.head.out.head._1.d.cloneType)
-    }
+    })
     val fpu = Flipped(new FPUCoreIO())
     //val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs))
     //val trace = Output(new TraceBundle)

src/main/scala/tile/VortexTile.scala

@@ -4,6 +4,7 @@
 package tile
 
 import chisel3._
+import chisel3.util.RRArbiter
 import org.chipsalliance.cde.config._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
@@ -88,30 +89,30 @@ class VortexTile private(
     beatBytes = lazyCoreParamsView.coreDataBytes,
     minLatency = 1)))*/
 
-  val imemNode = TLClientNode(Seq(TLMasterPortParameters.v1(
+  val imemNodes = Seq.tabulate(1) { i => TLClientNode(Seq(TLMasterPortParameters.v1(
     clients = Seq(TLMasterParameters.v1(
       sourceId = IdRange(0, 1 << 10), // TODO magic number
-      name = s"Vortex Core I-Mem",
+      name = s"Vortex Core ${vortexParams.hartId} I-Mem $i",
       requestFifo = true,
       supportsProbe = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
       supportsGet = TransferSizes(1, lazyCoreParamsView.coreDataBytes)
     ))
-  )))
+  )))}
 
-  val dmemNode = TLClientNode(Seq(TLMasterPortParameters.v1(
+  val dmemNodes = Seq.tabulate(4) { i => TLClientNode(Seq(TLMasterPortParameters.v1(
     clients = Seq(TLMasterParameters.v1(
       sourceId = IdRange(0, 1 << 10), // TODO magic number
-      name = s"Vortex Core D-Mem",
+      name = s"Vortex Core ${vortexParams.hartId} D-Mem Lane $i",
       requestFifo = true,
       supportsProbe = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
       supportsGet = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
       supportsPutFull = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
       supportsPutPartial = TransferSizes(1, lazyCoreParamsView.coreDataBytes)
     ))
-  )))
+  )))}
 
-  tlMasterXbar.node := imemNode
+  imemNodes.foreach { tlMasterXbar.node := _ }
-  tlMasterXbar.node := dmemNode
+  dmemNodes.foreach { tlMasterXbar.node := _ }
 
   val bus_error_unit = vortexParams.beuAddr map { a =>
     val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a)))
@@ -200,13 +201,32 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
   require(core.io.hartid.getWidth >= outer.hartIdSinkNode.bundle.getWidth,
     s"core hartid wire (${core.io.hartid.getWidth}b) truncates external hartid wire (${outer.hartIdSinkNode.bundle.getWidth}b)")
 
-  val (i_tl_out, _) = outer.imemNode.out.head
+  (core.io.imem zip outer.imemNodes).foreach { case (coreMem, tileNode) =>
-  val (d_tl_out, _) = outer.dmemNode.out.head
+    coreMem.d <> tileNode.out.head._1.d
+    coreMem.a <> tileNode.out.head._1.a
+  }
 
-  core.io.imem.a <> i_tl_out.a
+  val arb = Module(new RRArbiter(core.io.dmem.head.d.bits.source.cloneType, 4))
-  core.io.imem.d <> i_tl_out.d
+  val matchingSources = Wire(UInt(4.W))
-  core.io.dmem.a <> d_tl_out.a
+  val dmemDs = outer.dmemNodes.map(_.out.head._1.d)
-  core.io.dmem.d <> d_tl_out.d
+
+  (arb.io.in zip dmemDs).zipWithIndex.foreach { case ((arbIn, tileNode), i) =>
+    arbIn.valid := tileNode.valid
+    arbIn.bits := tileNode.bits.source
+    // assert(arbIn.ready, "source id arbiter should always be ready")
+  }
+  matchingSources := dmemDs.map(d => (d.bits.source === arb.io.out.bits) && arb.io.out.valid).asUInt
+  arb.io.out.ready := true.B
+
+  (core.io.dmem zip dmemDs).zipWithIndex.foreach { case ((coreMem, tileNode), i) =>
+    coreMem.d.bits := tileNode.bits
+    coreMem.d.valid := tileNode.valid && matchingSources(i)
+    tileNode.ready := coreMem.d.ready && matchingSources(i)
+  }
+
+  (core.io.dmem zip outer.dmemNodes).foreach { case (coreMem, tileNode) =>
+    coreMem.a <> tileNode.out.head._1.a
+  }
 
   core.io.fpu := DontCare