multilane support, args.bin ROM, verilog sources cleanup and vortex bump

src/main/scala/rocket/VortexCore.scala

@@ -34,16 +34,16 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
   addResource("/vsrc/vortex/hw/rtl/VX_dispatch.sv")
   addResource("/vsrc/vortex/hw/rtl/VX_issue.sv")
   // addResource("/vsrc/vortex/hw/rtl/cache/VX_shared_mem.sv")
-  addResource("/vsrc/vortex/hw/rtl/cache/VX_core_rsp_merge.sv")
-  addResource("/vsrc/vortex/hw/rtl/cache/VX_tag_access.sv")
-  addResource("/vsrc/vortex/hw/rtl/cache/VX_core_req_bank_sel.sv")
-  addResource("/vsrc/vortex/hw/rtl/cache/VX_bank.sv")
-  addResource("/vsrc/vortex/hw/rtl/cache/VX_cache.sv")
-  addResource("/vsrc/vortex/hw/rtl/cache/VX_data_access.sv")
+  // addResource("/vsrc/vortex/hw/rtl/cache/VX_core_rsp_merge.sv")
+  // addResource("/vsrc/vortex/hw/rtl/cache/VX_tag_access.sv")
+  // addResource("/vsrc/vortex/hw/rtl/cache/VX_core_req_bank_sel.sv")
+  // addResource("/vsrc/vortex/hw/rtl/cache/VX_bank.sv")
+  // addResource("/vsrc/vortex/hw/rtl/cache/VX_cache.sv")
+  // addResource("/vsrc/vortex/hw/rtl/cache/VX_data_access.sv")
   addResource("/vsrc/vortex/hw/rtl/cache/VX_cache_define.vh")
-  addResource("/vsrc/vortex/hw/rtl/cache/VX_flush_ctrl.sv")
-  addResource("/vsrc/vortex/hw/rtl/cache/VX_nc_bypass.sv")
-  addResource("/vsrc/vortex/hw/rtl/cache/VX_miss_resrv.sv")
+  // addResource("/vsrc/vortex/hw/rtl/cache/VX_flush_ctrl.sv")
+  // addResource("/vsrc/vortex/hw/rtl/cache/VX_nc_bypass.sv")
+  // addResource("/vsrc/vortex/hw/rtl/cache/VX_miss_resrv.sv")
   addResource("/vsrc/vortex/hw/rtl/VX_warp_sched.sv")
   // addResource("/vsrc/vortex/hw/rtl/Vortex.sv")
   addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_sat.sv")
@@ -69,16 +69,16 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
   addResource("/vsrc/vortex/hw/rtl/VX_trace_instr.vh")
   addResource("/vsrc/vortex/hw/rtl/VX_gpu_types.vh")
   addResource("/vsrc/vortex/hw/rtl/VX_config.vh")
-  addResource("/vsrc/vortex/hw/rtl/libs/VX_mux.sv")
+  // unused addResource("/vsrc/vortex/hw/rtl/libs/VX_mux.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_lzc.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_fifo_queue.sv")
-  addResource("/vsrc/vortex/hw/rtl/libs/VX_scope.sv")
+  // unused addResource("/vsrc/vortex/hw/rtl/libs/VX_scope.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_scan.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_find_first.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_multiplier.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_bits_remove.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_pipe_register.sv")
-  addResource("/vsrc/vortex/hw/rtl/libs/VX_onehot_mux.sv")
+  // unused addResource("/vsrc/vortex/hw/rtl/libs/VX_onehot_mux.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_priority_encoder.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_reset_relay.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_popcount.sv")
@@ -89,17 +89,17 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
   addResource("/vsrc/vortex/hw/rtl/libs/VX_index_buffer.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_onehot_encoder.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_matrix_arbiter.sv")
-  addResource("/vsrc/vortex/hw/rtl/libs/VX_divider.sv")
+  // unused addResource("/vsrc/vortex/hw/rtl/libs/VX_divider.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_dp_ram.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_axi_adapter.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_elastic_buffer.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_rr_arbiter.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_stream_arbiter.sv")
-  addResource("/vsrc/vortex/hw/rtl/libs/VX_bypass_buffer.sv")
+  // unused addResource("/vsrc/vortex/hw/rtl/libs/VX_bypass_buffer.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_sp_ram.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_stream_demux.sv")
-  addResource("/vsrc/vortex/hw/rtl/libs/VX_pending_size.sv")
-  addResource("/vsrc/vortex/hw/rtl/libs/VX_index_queue.sv")
+  // addResource("/vsrc/vortex/hw/rtl/libs/VX_pending_size.sv")
+  // unused addResource("/vsrc/vortex/hw/rtl/libs/VX_index_queue.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_serial_div.sv")
   addResource("/vsrc/vortex/hw/rtl/libs/VX_fair_arbiter.sv")
   addResource("/vsrc/vortex/hw/rtl/VX_define.vh")
@@ -110,10 +110,10 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
   addResource("/vsrc/vortex/hw/rtl/VX_execute.sv")
   addResource("/vsrc/vortex/hw/rtl/VX_fetch.sv")
   addResource("/vsrc/vortex/hw/rtl/VX_alu_unit.sv")
-  addResource("/vsrc/vortex/hw/rtl/VX_mem_arb.sv")
+  // unused addResource("/vsrc/vortex/hw/rtl/VX_mem_arb.sv")
   addResource("/vsrc/vortex/hw/rtl/VX_platform.vh")
   addResource("/vsrc/vortex/hw/rtl/VX_commit.sv")
-  addResource("/vsrc/vortex/hw/rtl/VX_smem_arb.sv")
+  // unused addResource("/vsrc/vortex/hw/rtl/VX_smem_arb.sv")
   addResource("/vsrc/vortex/hw/rtl/VX_pipeline.sv")
   addResource("/vsrc/vortex/hw/rtl/VX_lsu_unit.sv")
   // addResource("/vsrc/vortex/hw/rtl/VX_mem_unit.sv")
@@ -206,14 +206,14 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
     val hartid = Input(UInt(hartIdLen.W))
     val reset_vector = Input(UInt(resetVectorLen.W))
     val interrupts = Input(new CoreInterrupts())
-    val imem = new Bundle {
-      val a = tile.imemNode.out.head._1.a.cloneType
-      val d = Flipped(tile.imemNode.out.head._1.d.cloneType)
-    }
-    val dmem = new Bundle {
-      val a = tile.dmemNode.out.head._1.a.cloneType
-      val d = Flipped(tile.dmemNode.out.head._1.d.cloneType)
-    }
+    val imem = Vec(1, new Bundle { // TODO: magic number
+      val a = tile.imemNodes.head.out.head._1.a.cloneType
+      val d = Flipped(tile.imemNodes.head.out.head._1.d.cloneType)
+    })
+    val dmem = Vec(4, new Bundle {
+      val a = tile.dmemNodes.head.out.head._1.a.cloneType
+      val d = Flipped(tile.dmemNodes.head.out.head._1.d.cloneType)
+    })
     val fpu = Flipped(new FPUCoreIO())
     //val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs))
     //val trace = Output(new TraceBundle)