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Clarify confusing in/outResp naming in SourceGenerator

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This commit is contained in:
Hansung Kim
2023-10-15 23:17:01 -07:00
parent cbd32b78a9
commit 78012800e7
1 changed files with 10 additions and 5 deletions
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15
src/main/scala/tilelink/Coalescing.scala
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@@ -765,25 +765,30 @@ class CoalescerSourceGen(
respT: TLBundleD respT: TLBundleD
) extends Module { ) extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
// in/out means upstream/downstream
val inReq = Flipped(Decoupled(coalReqT.cloneType)) val inReq = Flipped(Decoupled(coalReqT.cloneType))
val outReq = Decoupled(coalReqT.cloneType) val outReq = Decoupled(coalReqT.cloneType)
val inResp = Flipped(Decoupled(respT.cloneType)) // no need for inResp, since CoalShiftQueue/Mono/MultiCoalescer only generates
// requests and do not take in responses. Coalesced responses are
// separately taken in by InflightTable.
val outResp = Flipped(Decoupled(respT.cloneType))
}) })
val sourceGen = Module( val sourceGen = Module(
new SourceGenerator(log2Ceil(config.numNewSrcIds), ignoreInUse = false) new SourceGenerator(log2Ceil(config.numNewSrcIds), ignoreInUse = false)
) )
sourceGen.io.gen := io.outReq.fire // use up a source ID only when request is created sourceGen.io.gen := io.outReq.fire // use up a source ID only when request is created
sourceGen.io.reclaim.valid := io.inResp.fire sourceGen.io.reclaim.valid := io.outResp.fire
sourceGen.io.reclaim.bits := io.inResp.bits.source sourceGen.io.reclaim.bits := io.outResp.bits.source
io.inResp.ready := true.B // should be always ready to reclaim old ID
// TODO: make sourceGen.io.reclaim Decoupled? // TODO: make sourceGen.io.reclaim Decoupled?
// passthrough logic
io.outReq <> io.inReq io.outReq <> io.inReq
// "man-in-the-middle" // "man-in-the-middle"
io.inReq.ready := io.outReq.ready && sourceGen.io.id.valid io.inReq.ready := io.outReq.ready && sourceGen.io.id.valid
// overwrite bits affected by sourcegen backpressure // overwrite bits affected by sourcegen backpressure
io.outReq.valid := io.inReq.valid && sourceGen.io.id.valid io.outReq.valid := io.inReq.valid && sourceGen.io.id.valid
io.outReq.bits.source := sourceGen.io.id.bits io.outReq.bits.source := sourceGen.io.id.bits
io.outResp.ready := true.B // should be always ready to reclaim old ID
} }
class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig)
@@ -902,7 +907,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig)
// //
val coalSourceGen = Module(new CoalescerSourceGen(config, coalReqT, tlCoal.d.bits)) val coalSourceGen = Module(new CoalescerSourceGen(config, coalReqT, tlCoal.d.bits))
coalSourceGen.io.inReq <> coalescer.io.coalReq coalSourceGen.io.inReq <> coalescer.io.coalReq
coalSourceGen.io.inResp <> tlCoal.d coalSourceGen.io.outResp <> tlCoal.d
// InflightTable IO // InflightTable IO
// //