Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics
This commit is contained in:
Richard Yan
@@ -4,7 +4,7 @@
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package tile
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import chisel3._
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import chisel3.util.RRArbiter
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import chisel3.util._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy._
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@@ -16,9 +16,7 @@ import freechips.rocketchip.util._
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import freechips.rocketchip.prci.ClockSinkParameters
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import freechips.rocketchip.regmapper.RegField
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import freechips.rocketchip.tile._
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import rocket.Vortex
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import scala.collection.mutable.ListBuffer
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import rocket.{Vortex, VortexBundleA, VortexBundleD}
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case class RocketTileBoundaryBufferParams(force: Boolean = false)
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@@ -35,26 +33,31 @@ case class VortexTileParams(
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blockerCtrlAddr: Option[BigInt] = None,
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clockSinkParams: ClockSinkParameters = ClockSinkParameters(),
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boundaryBuffers: Option[RocketTileBoundaryBufferParams] = None
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) extends InstantiableTileParams[VortexTile] {
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) extends InstantiableTileParams[VortexTile] {
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// require(icache.isDefined)
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// require(dcache.isDefined)
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// require(dcache.isDefined)
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def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): VortexTile = {
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def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(
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implicit p: Parameters
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): VortexTile = {
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new VortexTile(this, crossing, lookup)
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}
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}
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class VortexTile private(
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val vortexParams: VortexTileParams,
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crossing: ClockCrossingType,
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lookup: LookupByHartIdImpl,
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q: Parameters)
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extends BaseTile(vortexParams, crossing, lookup, q)
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class VortexTile private (
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val vortexParams: VortexTileParams,
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crossing: ClockCrossingType,
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lookup: LookupByHartIdImpl,
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q: Parameters
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) extends BaseTile(vortexParams, crossing, lookup, q)
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with SinksExternalInterrupts
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with SourcesExternalNotifications
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{
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with SourcesExternalNotifications {
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// Private constructor ensures altered LazyModule.p is used implicitly
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def this(params: VortexTileParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
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def this(
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params: VortexTileParams,
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crossing: TileCrossingParamsLike,
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lookup: LookupByHartIdImpl
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)(implicit p: Parameters) =
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this(params, crossing.crossingType, lookup, p)
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val intOutwardNode = IntIdentityNode()
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@@ -87,40 +90,70 @@ class VortexTile private(
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beatBytes = lazyCoreParamsView.coreDataBytes,
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minLatency = 1)))*/
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val imemNodes = Seq.tabulate(1) { i => TLClientNode(Seq(TLMasterPortParameters.v1(
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clients = Seq(TLMasterParameters.v1(
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sourceId = IdRange(0, 1 << 10), // TODO magic number
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name = s"Vortex Core ${vortexParams.hartId} I-Mem $i",
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requestFifo = true,
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supportsProbe = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
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supportsGet = TransferSizes(1, lazyCoreParamsView.coreDataBytes)
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))
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)))}
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val numLanes = 4 // TODO: use Parameters for this
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val sourceWidth = 4 // TODO: use Parameters for this
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val dmemNodes = Seq.tabulate(4) { i => TLClientNode(Seq(TLMasterPortParameters.v1(
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clients = Seq(TLMasterParameters.v1(
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sourceId = IdRange(0, 1 << 10), // TODO magic number
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name = s"Vortex Core ${vortexParams.hartId} D-Mem Lane $i",
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requestFifo = true,
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supportsProbe = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
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supportsGet = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
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supportsPutFull = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
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supportsPutPartial = TransferSizes(1, lazyCoreParamsView.coreDataBytes)
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))
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)))}
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val imemNodes = Seq.tabulate(1) { i =>
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TLClientNode(
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Seq(
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TLMasterPortParameters.v1(
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clients = Seq(
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TLMasterParameters.v1(
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sourceId = IdRange(0, 1 << sourceWidth),
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name = s"Vortex Core ${vortexParams.hartId} I-Mem $i",
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requestFifo = true,
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supportsProbe =
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TransferSizes(1, lazyCoreParamsView.coreDataBytes),
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supportsGet = TransferSizes(1, lazyCoreParamsView.coreDataBytes)
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)
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)
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)
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)
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)
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}
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val dmemNodes = Seq.tabulate(numLanes) { i =>
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TLClientNode(
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Seq(
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TLMasterPortParameters.v1(
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clients = Seq(
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TLMasterParameters.v1(
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sourceId = IdRange(0, 1 << sourceWidth),
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name = s"Vortex Core ${vortexParams.hartId} D-Mem Lane $i",
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requestFifo = true,
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supportsProbe =
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TransferSizes(1, lazyCoreParamsView.coreDataBytes),
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supportsGet = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
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supportsPutFull =
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TransferSizes(1, lazyCoreParamsView.coreDataBytes),
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supportsPutPartial =
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TransferSizes(1, lazyCoreParamsView.coreDataBytes)
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)
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)
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)
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)
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)
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}
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println(s"============= lazyCoreParamsView.coreDataBytes=${lazyCoreParamsView.coreDataBytes}")
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val memNode = TLClientNode(
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Seq(
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TLMasterPortParameters.v1(
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clients = Seq(
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TLMasterParameters.v1(
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sourceId = IdRange(0, 1 << sourceWidth),
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name = s"Vortex Core ${vortexParams.hartId} Mem Interface",
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requestFifo = true,
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supportsProbe = TransferSizes(16, 16), // FIXME: hardcoded
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supportsGet = TransferSizes(16, 16),
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supportsPutFull = TransferSizes(16, 16),
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supportsPutPartial = TransferSizes(16, 16)
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)
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)
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)
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)
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)
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val memNode = TLClientNode(Seq(TLMasterPortParameters.v1(
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clients = Seq(TLMasterParameters.v1(
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sourceId = IdRange(0, 1 << 15), // TODO magic numbers
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name = s"Vortex Core ${vortexParams.hartId} Mem Interface",
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requestFifo = true,
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supportsProbe = TransferSizes(16, 16),
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supportsGet = TransferSizes(16, 16),
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supportsPutFull = TransferSizes(16, 16),
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supportsPutPartial = TransferSizes(16, 16)
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)),
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)))
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if (vortexParams.useVxCache) {
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tlMasterXbar.node := TLWidthWidget(16) := memNode
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} else {
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@@ -131,7 +164,8 @@ class VortexTile private(
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/* below are copied from rocket */
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val bus_error_unit = vortexParams.beuAddr map { a =>
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val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a)))
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val beu =
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LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a)))
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intOutwardNode := beu.intNode
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connectTLSlave(beu.node, xBytes)
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beu
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@@ -139,13 +173,17 @@ class VortexTile private(
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val tile_master_blocker =
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tileParams.blockerCtrlAddr
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.map(BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true))
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.map(
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BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true)
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)
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.map(bp => LazyModule(new BasicBusBlocker(bp)))
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tile_master_blocker.foreach(lm => connectTLSlave(lm.controlNode, xBytes))
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// TODO: this doesn't block other masters, e.g. RoCCs
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tlOtherMastersNode := tile_master_blocker.map { _.node := tlMasterXbar.node } getOrElse { tlMasterXbar.node }
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tlOtherMastersNode := tile_master_blocker.map {
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_.node := tlMasterXbar.node
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} getOrElse { tlMasterXbar.node }
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masterNode :=* tlOtherMastersNode
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DisableMonitors { implicit p => tlSlaveXbar.node :*= slaveNode }
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@@ -163,7 +201,6 @@ class VortexTile private(
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Description(name, mapping ++ cpuProperties ++ nextLevelCacheProperty
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++ tileProperties ++ dtimProperty ++ itimProperty ++ beuProperty)
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}
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}
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ResourceBinding {
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Resource(cpuDevice, "reg").bind(ResourceAddress(staticIdForMetadataUseOnly))
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@@ -171,15 +208,33 @@ class VortexTile private(
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override lazy val module = new VortexTileModuleImp(this)
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override def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (vortexParams.boundaryBuffers, crossing) match {
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case (Some(RocketTileBoundaryBufferParams(true )), _) => TLBuffer()
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case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1))
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override def makeMasterBoundaryBuffers(
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crossing: ClockCrossingType
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)(implicit p: Parameters) = (vortexParams.boundaryBuffers, crossing) match {
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case (Some(RocketTileBoundaryBufferParams(true)), _) => TLBuffer()
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case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) =>
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TLBuffer(
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BufferParams.none,
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BufferParams.flow,
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BufferParams.none,
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BufferParams.flow,
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BufferParams(1)
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)
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case _ => TLBuffer(BufferParams.none)
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}
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override def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = (vortexParams.boundaryBuffers, crossing) match {
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case (Some(RocketTileBoundaryBufferParams(true )), _) => TLBuffer()
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case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) => TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none)
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override def makeSlaveBoundaryBuffers(
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crossing: ClockCrossingType
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)(implicit p: Parameters) = (vortexParams.boundaryBuffers, crossing) match {
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case (Some(RocketTileBoundaryBufferParams(true)), _) => TLBuffer()
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case (Some(RocketTileBoundaryBufferParams(false)), _: RationalCrossing) =>
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TLBuffer(
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BufferParams.flow,
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BufferParams.none,
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BufferParams.none,
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BufferParams.none,
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BufferParams.none
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)
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case _ => TLBuffer(BufferParams.none)
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}
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}
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@@ -188,7 +243,7 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
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Annotated.params(this, outer.vortexParams)
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val core = Module(new Vortex(outer)(outer.p))
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core.io.clock := clock
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core.io.reset := reset
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@@ -200,8 +255,7 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
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)
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// Report when the tile has ceased to retire instructions; for now the only cause is clock gating
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outer.reportCease(outer.vortexParams.core.clockGate.option(
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core.io.cease))
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outer.reportCease(outer.vortexParams.core.clockGate.option(core.io.cease))
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outer.reportWFI(Some(core.io.wfi))
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@@ -223,49 +277,103 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
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// require(core.io.hartid.getWidth >= outer.hartIdSinkNode.bundle.getWidth,
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// s"core hartid wire (${core.io.hartid.getWidth}b) truncates external hartid wire (${outer.hartIdSinkNode.bundle.getWidth}b)")
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// ---------------------------------------------
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// Translate Vortex memory interface to TileLink
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// ---------------------------------------------
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if (outer.vortexParams.useVxCache) {
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println(s"width of a channel data ${core.io.mem.get.a.bits.data.getWidth}")
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println(s"width of d channel data ${core.io.mem.get.d.bits.data.getWidth}")
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core.io.mem.get.a <> outer.memNode.out.head._1.a
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core.io.mem.get.d <> outer.memNode.out.head._1.d
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}
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else {
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(core.io.imem.get zip outer.imemNodes).foreach { case (coreMem, tileNode) =>
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coreMem.d <> tileNode.out.head._1.d
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coreMem.a <> tileNode.out.head._1.a
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}
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// pick source id and:
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val memTLAdapter = Module(new VortexTLAdapter(
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outer.sourceWidth,
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chiselTypeOf(core.io.mem.get.a.bits),
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chiselTypeOf(core.io.mem.get.d.bits),
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chiselTypeOf(outer.memNode.out.head._1.a.bits),
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chiselTypeOf(outer.memNode.out.head._1.d.bits),
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))
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// connection: VortexBundle <--> VortexTLAdapter <--> TL memNode
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memTLAdapter.io.inReq <> core.io.mem.get.a
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core.io.mem.get.d <> memTLAdapter.io.inResp
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outer.memNode.out(0)._1.a <> memTLAdapter.io.outReq
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memTLAdapter.io.outResp <> outer.memNode.out(0)._1.d
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// core.io.mem.get.a <> outer.memNode.out.head._1.a
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// core.io.mem.get.d <> outer.memNode.out.head._1.d
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} else {
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val imemTLAdapter = Module(new VortexTLAdapter(
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outer.sourceWidth,
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chiselTypeOf(core.io.imem.get(0).a.bits),
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chiselTypeOf(core.io.imem.get(0).d.bits),
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chiselTypeOf(outer.imemNodes.head.out.head._1.a.bits),
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chiselTypeOf(outer.imemNodes.head.out.head._1.d.bits),
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))
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// TODO: make imemNodes not a vector
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imemTLAdapter.io.inReq <> core.io.imem.get(0).a
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core.io.imem.get(0).d <> imemTLAdapter.io.inResp
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outer.imemNodes(0).out(0)._1.a <> imemTLAdapter.io.outReq
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imemTLAdapter.io.outResp <> outer.imemNodes(0).out(0)._1.d
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// Since the individual per-lane TL requests might come back out-of-sync between
|
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// the lanes, but Vortex core expects the lane requests to be synced,
|
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// we need to selectively fire responses that have the same source, and
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// delay others. Below is the logic that implements this.
|
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|
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// choose one source out of the arriving per-lane TL D channels
|
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val arb = Module(
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new RRArbiter(core.io.dmem.get.head.d.bits.source.cloneType, outer.numLanes)
|
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)
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val dmemTLBundles = outer.dmemNodes.map(_.out.head._1)
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arb.io.out.ready := true.B
|
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(arb.io.in zip dmemTLBundles).foreach { case (arbIn, tlBundle) =>
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arbIn.valid := tlBundle.d.valid
|
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arbIn.bits := tlBundle.d.bits.source
|
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}
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val matchingSources = Wire(UInt(outer.numLanes.W))
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matchingSources := dmemTLBundles
|
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.map(b => (b.d.bits.source === arb.io.out.bits) && arb.io.out.valid)
|
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.asUInt
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|
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// connection: VortexBundle <--> VortexTLAdapter <--> dmemNodes
|
||||
// @perf: this would duplicate SourceGenerator table for every lane and eat
|
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// up some area
|
||||
val dmemTLAdapters = Seq.tabulate(outer.numLanes) { _ =>
|
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Module(new VortexTLAdapter(
|
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outer.sourceWidth,
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chiselTypeOf(core.io.dmem.get(0).a.bits),
|
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chiselTypeOf(core.io.dmem.get(0).d.bits),
|
||||
chiselTypeOf(dmemTLBundles.head.a.bits),
|
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chiselTypeOf(dmemTLBundles.head.d.bits),
|
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))
|
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}
|
||||
(core.io.dmem.get zip dmemTLAdapters) foreach { case (coreMem, tlAdapter) =>
|
||||
tlAdapter.io.inReq <> coreMem.a
|
||||
coreMem.d <> tlAdapter.io.inResp
|
||||
}
|
||||
(dmemTLAdapters zip dmemTLBundles) foreach { case (tlAdapter, tlBundle) =>
|
||||
tlBundle.a <> tlAdapter.io.outReq
|
||||
}
|
||||
// using the chosen source id,
|
||||
// - lie to core that response is not valid if source doesn't match picked
|
||||
// - lie to downstream that core is not ready if source doesn't match picked
|
||||
|
||||
val arb = Module(new RRArbiter(core.io.dmem.get.head.d.bits.source.cloneType, 4))
|
||||
val matchingSources = Wire(UInt(4.W))
|
||||
val dmemDs = outer.dmemNodes.map(_.out.head._1.d)
|
||||
|
||||
(arb.io.in zip dmemDs).zipWithIndex.foreach { case ((arbIn, tileNode), i) =>
|
||||
arbIn.valid := tileNode.valid
|
||||
arbIn.bits := tileNode.bits.source
|
||||
}
|
||||
matchingSources := dmemDs.map(d => (d.bits.source === arb.io.out.bits) && arb.io.out.valid).asUInt
|
||||
arb.io.out.ready := true.B
|
||||
|
||||
(core.io.dmem.get zip dmemDs).zipWithIndex.foreach { case ((coreMem, tileNode), i) =>
|
||||
coreMem.d.bits := tileNode.bits
|
||||
coreMem.d.valid := tileNode.valid && matchingSources(i)
|
||||
tileNode.ready := coreMem.d.ready && matchingSources(i)
|
||||
(dmemTLAdapters zip dmemTLBundles).zipWithIndex.foreach {
|
||||
case ((tlAdapter, tlBundle), i) =>
|
||||
tlAdapter.io.outResp.bits := tlBundle.d.bits
|
||||
tlAdapter.io.outResp.valid := tlBundle.d.valid && matchingSources(i)
|
||||
tlBundle.d.ready := tlAdapter.io.outResp.ready && matchingSources(i)
|
||||
}
|
||||
|
||||
(core.io.dmem.get zip outer.dmemNodes).foreach { case (coreMem, tileNode) =>
|
||||
coreMem.a <> tileNode.out.head._1.a
|
||||
}
|
||||
// (core.io.dmem.get zip outer.dmemNodes).foreach { case (coreMem, tileNode) =>
|
||||
// tileNode.out.head._1.a <> coreMem.a
|
||||
// }
|
||||
}
|
||||
|
||||
// core.io.fpu := DontCare
|
||||
|
||||
// TODO eliminate this redundancy
|
||||
// val h = dcachePorts.size
|
||||
//val c = core.dcacheArbPorts
|
||||
// val c = core.dcacheArbPorts
|
||||
// val o = outer.nDCachePorts
|
||||
// require(h == c, s"port list size was $h, core expected $c")
|
||||
// require(h == o, s"port list size was $h, outer counted $o")
|
||||
@@ -273,7 +381,61 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
|
||||
// dcacheArb.io.requestor <> dcachePorts.toSeq
|
||||
}
|
||||
|
||||
// Some @copypaste from CoalescerSourceGen.
|
||||
class VortexTLAdapter(
|
||||
newSourceWidth: Int,
|
||||
inReqT: VortexBundleA,
|
||||
inRespT: VortexBundleD,
|
||||
outReqT: TLBundleA,
|
||||
outRespT: TLBundleD
|
||||
) extends Module {
|
||||
val io = IO(new Bundle {
|
||||
// in/out means upstream/downstream
|
||||
val inReq = Flipped(Decoupled(inReqT))
|
||||
val outReq = Decoupled(outReqT)
|
||||
val inResp = Decoupled(inRespT)
|
||||
val outResp = Flipped(Decoupled(outRespT))
|
||||
})
|
||||
val sourceGen = Module(new SourceGenerator(
|
||||
newSourceWidth,
|
||||
Some(inReqT.source),
|
||||
ignoreInUse = false
|
||||
))
|
||||
sourceGen.io.gen := io.outReq.fire // use up a source ID only when request is created
|
||||
sourceGen.io.reclaim.valid := io.outResp.fire
|
||||
sourceGen.io.reclaim.bits := io.outResp.bits.source
|
||||
sourceGen.io.meta := io.inReq.bits.source
|
||||
|
||||
// io passthrough logic
|
||||
// TLBundleA <> VortexBundleA
|
||||
io.outReq.valid := io.inReq.valid
|
||||
io.outReq.bits.opcode := io.inReq.bits.opcode
|
||||
io.outReq.bits.param := 0.U
|
||||
io.outReq.bits.size := io.inReq.bits.size
|
||||
io.outReq.bits.source := io.inReq.bits.source
|
||||
io.outReq.bits.address := io.inReq.bits.address
|
||||
io.outReq.bits.mask := io.inReq.bits.mask
|
||||
io.outReq.bits.data := io.inReq.bits.data
|
||||
io.outReq.bits.corrupt := 0.U
|
||||
io.inReq.ready := io.outReq.ready
|
||||
// VortexBundleD <> TLBundleD
|
||||
io.inResp.valid := io.outResp.valid
|
||||
io.inResp.bits.opcode := io.outResp.bits.opcode
|
||||
io.inResp.bits.size := io.outResp.bits.size
|
||||
io.inResp.bits.source := io.outResp.bits.source
|
||||
io.inResp.bits.data := io.outResp.bits.data
|
||||
io.outResp.ready := io.inResp.ready
|
||||
|
||||
// "man-in-the-middle"
|
||||
io.inReq.ready := io.outReq.ready && sourceGen.io.id.valid
|
||||
io.outReq.valid := io.inReq.valid && sourceGen.io.id.valid
|
||||
io.outReq.bits.source := sourceGen.io.id.bits
|
||||
// translate upstream response back to its old sourceId
|
||||
io.inResp.bits.source := sourceGen.io.peek
|
||||
}
|
||||
|
||||
// FIXME: unsure this is necessary
|
||||
trait HasFpuOpt { this: RocketTileModuleImp =>
|
||||
val fpuOpt = outer.tileParams.core.fpu.map(params => Module(new FPU(params)(outer.p)))
|
||||
val fpuOpt =
|
||||
outer.tileParams.core.fpu.map(params => Module(new FPU(params)(outer.p)))
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user