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Fix ChiselEnum experimental warning

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This commit is contained in:
Hansung Kim
2023-05-11 16:20:01 -07:00
parent 0c8909cb43
commit 772deda9c2
1 changed files with 6 additions and 8 deletions
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14
src/main/scala/tilelink/Coalescing.scala
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@@ -4,7 +4,6 @@ package freechips.rocketchip.tilelink
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import chisel3.experimental.ChiselEnum
import org.chipsalliance.cde.config.{Parameters, Field} import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
// import freechips.rocketchip.devices.tilelink.TLTestRAM // import freechips.rocketchip.devices.tilelink.TLTestRAM
@@ -381,9 +380,9 @@ class CoalShiftQueue[T <: Data](gen: T, entries: Int, config: CoalescerConfig)
// Software model: coalescer.py // Software model: coalescer.py
class MonoCoalescer( class MonoCoalescer(
config: CoalescerConfig,
coalLogSize: Int, coalLogSize: Int,
windowT: CoalShiftQueue[NonCoalescedRequest], windowT: CoalShiftQueue[NonCoalescedRequest]
config: CoalescerConfig
) extends Module { ) extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
val window = Input(windowT.io.cloneType) val window = Input(windowT.io.cloneType)
@@ -532,9 +531,9 @@ class MonoCoalescer(
// //
// Software model: coalescer.py // Software model: coalescer.py
class MultiCoalescer( class MultiCoalescer(
config: CoalescerConfig,
windowT: CoalShiftQueue[NonCoalescedRequest], windowT: CoalShiftQueue[NonCoalescedRequest],
coalReqT: Request, coalReqT: Request,
config: CoalescerConfig
) extends Module { ) extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
// coalescing window, connected to the contents of the request queues // coalescing window, connected to the contents of the request queues
@@ -549,7 +548,7 @@ class MultiCoalescer(
}) })
val coalescers = config.coalLogSizes.map(size => val coalescers = config.coalLogSizes.map(size =>
Module(new MonoCoalescer(size, windowT, config)) Module(new MonoCoalescer(config, size, windowT))
) )
coalescers.foreach(_.io.window := io.window) coalescers.foreach(_.io.window := io.window)
@@ -704,14 +703,13 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig)
) )
val oldSourceWidth = outer.cpuNode.in.head._1.params.sourceBits val oldSourceWidth = outer.cpuNode.in.head._1.params.sourceBits
// note we are using word size. assuming all coalescer inputs are word sized
val reqQueueEntryT = new NonCoalescedRequest(config) val reqQueueEntryT = new NonCoalescedRequest(config)
val reqQueues = Module( val reqQueues = Module(
new CoalShiftQueue(reqQueueEntryT, config.queueDepth, config) new CoalShiftQueue(reqQueueEntryT, config.queueDepth, config)
) )
val coalReqT = new CoalescedRequest(config) val coalReqT = new CoalescedRequest(config)
val coalescer = Module(new MultiCoalescer(reqQueues, coalReqT, config)) val coalescer = Module(new MultiCoalescer(config, reqQueues, coalReqT))
coalescer.io.window := reqQueues.io coalescer.io.window := reqQueues.io
reqQueues.io.coalescable := coalescer.io.coalescable reqQueues.io.coalescable := coalescer.io.coalescable
reqQueues.io.invalidate := coalescer.io.invalidate reqQueues.io.invalidate := coalescer.io.invalidate
@@ -955,7 +953,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig)
} }
class Uncoalescer(config: CoalescerConfig) extends Module { class Uncoalescer(config: CoalescerConfig) extends Module {
// notes to hansung: // Mapping to reference model param names
// val numLanes: Int, <-> config.NUM_LANES // val numLanes: Int, <-> config.NUM_LANES
// val numPerLaneReqs: Int, <-> config.DEPTH // val numPerLaneReqs: Int, <-> config.DEPTH
// val sourceWidth: Int, <-> log2ceil(config.NUM_OLD_IDS) // val sourceWidth: Int, <-> log2ceil(config.NUM_OLD_IDS)