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Intergation of L1 Fatbank

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This commit is contained in:
Vamber Yang
2023-10-31 16:14:34 -07:00
parent 635f4e42ff 60a63d4e11
commit 75adb1dc66
4 changed files with 578 additions and 6 deletions
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35
src/main/scala/tilelink/CanHaveMemtraceCore.scala
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@@ -3,6 +3,8 @@ package freechips.rocketchip.tilelink
import freechips.rocketchip.diplomacy.LazyModule
import freechips.rocketchip.subsystem.BaseSubsystem
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket
// TODO: possibly move to somewhere closer to CoalescingUnit
// TODO: separate coalescer config from CanHaveMemtraceCore
@@ -44,16 +46,39 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
}
case None => tracer.node
}
val upstream = p(CoalXbarKey) match {
val coalXbar = p(CoalXbarKey) match {
case Some(xbarParam) =>{
val priorityXbar = LazyModule(new CoalescerTLPriortyXBar)
println(s"============ Using Priority XBar for Coalescer Requests ")
priorityXbar.node :=* coalescerNode
priorityXbar.node
val coXbar = LazyModule(new TLXbar)
println(s"============ Using TLXBar for Coalescer Requests ")
coXbar.node :=* coalescerNode
coXbar.node
}
case None => coalescerNode
}
val vortexBank = p(VortexFatBankKey) match {
case Some(fatBankParam) =>{
val vx_fatbank = LazyModule(new VortexFatBank(fatBankParam))
println(s"============ Using Vortex FatBank as L1 ")
vx_fatbank.coalToVxCacheNode :=* coalXbar
vx_fatbank.vxCacheToL2Node
}
case None => coalXbar
}
//If there is only 1 bank, the code below is useless
val upstream = p(CoalXbarKey) match {
case Some(xbarParam) =>{
val tileXbar = LazyModule(new TLXbar)
println(s"============ Using TLXBar for L1 Requests ")
tileXbar.node :=* vortexBank
tileXbar.node
}
case None => vortexBank
}
sbus.coupleFrom(s"gpu-tracer") { _ :=* upstream }
}
}