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Enable configuring MSHR size from Chisel

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This commit is contained in:
Hansung Kim
2023-11-28 19:55:08 -08:00
parent f8d7169d19
commit 74fe530105
1 changed files with 5 additions and 1 deletions
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6
src/main/scala/rocket/VortexBank.scala
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@@ -23,6 +23,10 @@ case class VortexL1Config(
def coreTagPlusSizeWidth: Int = { def coreTagPlusSizeWidth: Int = {
log2Ceil(wordSize) + coreTagWidth log2Ceil(wordSize) + coreTagWidth
} }
// NOTE: This assertion depends on the fact that the Vortex cache is
// configured to have 1 bank, and that it uses MSHR id as the tag of
// memory-side requests. Otherwise, it will append bank id to the tag as
// well and break this requirement.
require( require(
mshrSize == memSideSourceIds, mshrSize == memSideSourceIds,
"MSHR size must match the number of sourceIds to downstream." "MSHR size must match the number of sourceIds to downstream."
@@ -214,7 +218,7 @@ class VortexBankImp(
WORD_SIZE = config.wordSize, WORD_SIZE = config.wordSize,
CACHE_LINE_SIZE = config.cacheLineSize, CACHE_LINE_SIZE = config.cacheLineSize,
CORE_TAG_WIDTH = config.coreTagPlusSizeWidth, CORE_TAG_WIDTH = config.coreTagPlusSizeWidth,
// MSHR_SIZE = config.mshrSize MSHR_SIZE = config.mshrSize
// NUM_BANKS is set to 1 to treat a whole VX_cache_top instance as a // NUM_BANKS is set to 1 to treat a whole VX_cache_top instance as a
// single bank // single bank
) )