From 69bf554d0f3b2b171e4013e4fbbffa196f36a4a8 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Fri, 19 Jan 2024 18:25:03 -0800 Subject: [PATCH] Split SimMem verilog constants to a .vh file --- src/main/resources/vsrc/SimDefaults.vh | 4 +++ src/main/resources/vsrc/SimMemTrace.v | 25 ++++++------- src/main/resources/vsrc/SimMemTraceLogger.v | 36 +++++++++---------- .../scala/radiance/memory/Coalescing.scala | 2 ++ 4 files changed, 33 insertions(+), 34 deletions(-) create mode 100644 src/main/resources/vsrc/SimDefaults.vh diff --git a/src/main/resources/vsrc/SimDefaults.vh b/src/main/resources/vsrc/SimDefaults.vh new file mode 100644 index 0000000..c939ad0 --- /dev/null +++ b/src/main/resources/vsrc/SimDefaults.vh @@ -0,0 +1,4 @@ +`define SIMMEM_DATA_WIDTH 64 +`define MAX_NUM_LANES 32 +`define SIMMEM_SOURCE_WIDTH 32 +`define SIMMEM_LOGSIZE_WIDTH 8 diff --git a/src/main/resources/vsrc/SimMemTrace.v b/src/main/resources/vsrc/SimMemTrace.v index f47d556..8ca8e87 100644 --- a/src/main/resources/vsrc/SimMemTrace.v +++ b/src/main/resources/vsrc/SimMemTrace.v @@ -1,7 +1,4 @@ -// FIXME hardcoded -`define MEMTRACE_DATA_WIDTH 64 -`define MAX_NUM_LANES 32 -`define MEMTRACE_LOGSIZE_WIDTH 8 +`include "SimDefaults.vh" import "DPI-C" function void memtrace_init( input string filename, @@ -36,16 +33,16 @@ module SimMemTrace #(parameter FILENAME = "undefined", // These have to match the IO port name of the Chisel wrapper module. input trace_read_ready, output [NUM_LANES-1:0] trace_read_valid, - output [`MEMTRACE_DATA_WIDTH*NUM_LANES-1:0] trace_read_address, + output [`SIMMEM_DATA_WIDTH*NUM_LANES-1:0] trace_read_address, output [NUM_LANES-1:0] trace_read_is_store, - output [`MEMTRACE_LOGSIZE_WIDTH*NUM_LANES-1:0] trace_read_size, - output [`MEMTRACE_DATA_WIDTH*NUM_LANES-1:0] trace_read_data, + output [`SIMMEM_LOGSIZE_WIDTH*NUM_LANES-1:0] trace_read_size, + output [`SIMMEM_DATA_WIDTH*NUM_LANES-1:0] trace_read_data, output trace_read_finished ); bit __in_valid [NUM_LANES-1:0]; longint __in_address [NUM_LANES-1:0]; bit __in_is_store [NUM_LANES-1:0]; - reg [`MEMTRACE_LOGSIZE_WIDTH-1:0] __in_size [NUM_LANES-1:0]; + reg [`SIMMEM_LOGSIZE_WIDTH-1:0] __in_size [NUM_LANES-1:0]; longint __in_data [NUM_LANES-1:0]; bit __in_finished; @@ -53,11 +50,11 @@ module SimMemTrace #(parameter FILENAME = "undefined", generate for (g = 0; g < NUM_LANES; g = g + 1) begin assign trace_read_valid[g] = __in_valid[g]; - assign trace_read_address[`MEMTRACE_DATA_WIDTH*(g+1)-1:`MEMTRACE_DATA_WIDTH*g] = __in_address[g]; + assign trace_read_address[`SIMMEM_DATA_WIDTH*(g+1)-1:`SIMMEM_DATA_WIDTH*g] = __in_address[g]; assign trace_read_is_store[g] = __in_is_store[g]; - assign trace_read_size[`MEMTRACE_LOGSIZE_WIDTH*(g+1)-1:`MEMTRACE_LOGSIZE_WIDTH*g] = __in_size[g]; - assign trace_read_data[`MEMTRACE_DATA_WIDTH*(g+1)-1:`MEMTRACE_DATA_WIDTH*g] = __in_data[g]; + assign trace_read_size[`SIMMEM_LOGSIZE_WIDTH*(g+1)-1:`SIMMEM_LOGSIZE_WIDTH*g] = __in_size[g]; + assign trace_read_data[`SIMMEM_DATA_WIDTH*(g+1)-1:`SIMMEM_DATA_WIDTH*g] = __in_data[g]; end endgenerate assign trace_read_finished = __in_finished; @@ -71,11 +68,11 @@ module SimMemTrace #(parameter FILENAME = "undefined", if (reset) begin for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin __in_valid[tid] = 1'b0; - __in_address[tid] = `MEMTRACE_DATA_WIDTH'b0; + __in_address[tid] = `SIMMEM_DATA_WIDTH'b0; __in_is_store[tid] = 1'b0; - __in_size[tid] = `MEMTRACE_LOGSIZE_WIDTH'b0; - __in_data[tid] = `MEMTRACE_DATA_WIDTH'b0; + __in_size[tid] = `SIMMEM_LOGSIZE_WIDTH'b0; + __in_data[tid] = `SIMMEM_DATA_WIDTH'b0; end __in_finished = 1'b0; end else begin diff --git a/src/main/resources/vsrc/SimMemTraceLogger.v b/src/main/resources/vsrc/SimMemTraceLogger.v index 03839df..40b75f1 100644 --- a/src/main/resources/vsrc/SimMemTraceLogger.v +++ b/src/main/resources/vsrc/SimMemTraceLogger.v @@ -1,8 +1,4 @@ -// FIXME hardcoded -`define DATA_WIDTH 64 -`define MAX_NUM_LANES 32 -`define SOURCEID_WIDTH 32 -`define LOGSIZE_WIDTH 8 +`include "SimDefaults.vh" import "DPI-C" function int memtracelogger_init( input bit is_response, @@ -38,11 +34,11 @@ module SimMemTraceLogger #(parameter // NOTE: LSB is lane 0 input [NUM_LANES-1:0] trace_log_valid, - input [`SOURCEID_WIDTH*NUM_LANES-1:0] trace_log_source, - input [`DATA_WIDTH*NUM_LANES-1:0] trace_log_address, + input [`SIMMEM_SOURCE_WIDTH*NUM_LANES-1:0] trace_log_source, + input [`SIMMEM_DATA_WIDTH*NUM_LANES-1:0] trace_log_address, input [NUM_LANES-1:0] trace_log_is_store, - input [`LOGSIZE_WIDTH*NUM_LANES-1:0] trace_log_size, - input [`DATA_WIDTH*NUM_LANES-1:0] trace_log_data, + input [`SIMMEM_LOGSIZE_WIDTH*NUM_LANES-1:0] trace_log_size, + input [`SIMMEM_DATA_WIDTH*NUM_LANES-1:0] trace_log_data, output trace_log_ready ); int logger_handle; @@ -50,17 +46,17 @@ module SimMemTraceLogger #(parameter // cycle_counter will start off right after reset is deasserted which should // synchronize itself with SimMemTrace.cycle_counter - reg [`DATA_WIDTH-1:0] cycle_counter; - wire [`DATA_WIDTH-1:0] next_cycle_counter; + reg [`SIMMEM_DATA_WIDTH-1:0] cycle_counter; + wire [`SIMMEM_DATA_WIDTH-1:0] next_cycle_counter; assign next_cycle_counter = cycle_counter + 1'b1; // wires going into the DPC wire __valid [NUM_LANES-1:0]; - wire [`SOURCEID_WIDTH-1:0] __source [NUM_LANES-1:0]; - wire [`DATA_WIDTH-1:0] __address [NUM_LANES-1:0]; + wire [`SIMMEM_SOURCE_WIDTH-1:0] __source [NUM_LANES-1:0]; + wire [`SIMMEM_DATA_WIDTH-1:0] __address [NUM_LANES-1:0]; wire __is_store [NUM_LANES-1:0]; - wire [`LOGSIZE_WIDTH-1:0] __size [NUM_LANES-1:0]; - wire [`DATA_WIDTH-1:0] __data [NUM_LANES-1:0]; + wire [`SIMMEM_LOGSIZE_WIDTH-1:0] __size [NUM_LANES-1:0]; + wire [`SIMMEM_DATA_WIDTH-1:0] __data [NUM_LANES-1:0]; assign trace_log_ready = __in_ready; @@ -69,11 +65,11 @@ module SimMemTraceLogger #(parameter for (g = 0; g < NUM_LANES; g = g + 1) begin // LSB is lane 0 assign __valid[g] = trace_log_valid[g]; - assign __source[g] = trace_log_source[`SOURCEID_WIDTH*(g+1)-1:`SOURCEID_WIDTH*g]; - assign __address[g] = trace_log_address[`DATA_WIDTH*(g+1)-1:`DATA_WIDTH*g]; + assign __source[g] = trace_log_source[`SIMMEM_SOURCE_WIDTH*(g+1)-1:`SIMMEM_SOURCE_WIDTH*g]; + assign __address[g] = trace_log_address[`SIMMEM_DATA_WIDTH*(g+1)-1:`SIMMEM_DATA_WIDTH*g]; assign __is_store[g] = trace_log_is_store[g]; - assign __size[g] = trace_log_size[`LOGSIZE_WIDTH*(g+1)-1:`LOGSIZE_WIDTH*g]; - assign __data[g] = trace_log_data[`DATA_WIDTH*(g+1)-1:`DATA_WIDTH*g]; + assign __size[g] = trace_log_size[`SIMMEM_LOGSIZE_WIDTH*(g+1)-1:`SIMMEM_LOGSIZE_WIDTH*g]; + assign __data[g] = trace_log_data[`SIMMEM_DATA_WIDTH*(g+1)-1:`SIMMEM_DATA_WIDTH*g]; end endgenerate @@ -85,7 +81,7 @@ module SimMemTraceLogger #(parameter always @(posedge clock) begin if (reset) begin __in_ready = 1'b1; - cycle_counter <= `DATA_WIDTH'b0; + cycle_counter <= `SIMMEM_DATA_WIDTH'b0; end else begin cycle_counter <= next_cycle_counter; diff --git a/src/main/scala/radiance/memory/Coalescing.scala b/src/main/scala/radiance/memory/Coalescing.scala index 0018394..f3b2ca9 100644 --- a/src/main/scala/radiance/memory/Coalescing.scala +++ b/src/main/scala/radiance/memory/Coalescing.scala @@ -1731,6 +1731,7 @@ class SimMemTrace(filename: String, numLanes: Int, traceHasSource: Boolean) } }) + addResource("/vsrc/SimDefaults.vh") addResource("/vsrc/SimMemTrace.v") addResource("/csrc/SimMemTrace.cc") addResource("/csrc/SimMemTrace.h") @@ -2006,6 +2007,7 @@ class SimMemTraceLogger( } }) + addResource("/vsrc/SimDefaults.vh") addResource("/vsrc/SimMemTraceLogger.v") addResource("/csrc/SimMemTraceLogger.cc") addResource("/csrc/SimMemTrace.h")