From 6755cb3eeca31197f0b3ceaea6754d6393038388 Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Mon, 8 May 2023 00:49:30 -0700
Subject: [PATCH] Lax traceReadCycle advancing logic

Trying to advance trace cycle while downstream is blocking
is tricky because DPI call is synchronous, and that gives
timing difference between the line we have fired to downstream
and the current cycle counter we maintain.
Just stall the counter whenever downstream is not ready
for now.
---
 src/main/scala/tilelink/Coalescing.scala | 26 +++++++++++-------------
 1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala
index 4895cc0..62c0473 100644
--- a/src/main/scala/tilelink/Coalescing.scala
+++ b/src/main/scala/tilelink/Coalescing.scala
@@ -1105,22 +1105,20 @@ class MemTraceDriverImp(outer: MemTraceDriver, config: CoalescerConfig, traceFil
     req.data := sim.io.trace_read.data(dataW * (i + 1) - 1, dataW * i)
   }
 
-  def missedLine = {
-    val existsValidLine = WireInit(false.B)
-    existsValidLine := laneReqs.map(_.valid).reduce(_||_)
-    val missedLine = WireInit(false.B)
-    missedLine := !downstreamReady && existsValidLine
+  // def missedLine = {
+  //   val existsValidLine = WireInit(false.B)
+  //   existsValidLine := laneReqs.map(_.valid).reduce(_||_)
+  //   val missedLine = WireInit(false.B)
+  //   missedLine := !downstreamReady && existsValidLine
 
-    // Debug
-    dontTouch(downstreamReady)
-    dontTouch(existsValidLine)
-    dontTouch(missedLine)
+  //   // Debug
+  //   dontTouch(downstreamReady)
+  //   dontTouch(existsValidLine)
+  //   dontTouch(missedLine)
 
-    missedLine
-  }
-  // Do not increment trace read cycle if we didn't fire a valid line because
-  // downstream was blocking.  This prevents missing any line in the trace.
-  when (!missedLine){
+  //   missedLine
+  // }
+  when (downstreamReady){
     traceReadCycle := traceReadCycle + 1.U
   }