Parameterize SimMemTrace Verilog module to number of threads

src/main/resources/vsrc/SimMemTrace.v

@@ -1,65 +1,90 @@
 `define DATA_WIDTH 64
+`define MAX_NUM_THREADS 32
 
 import "DPI-C" function void memtrace_init(
-    input  string  filename
+  input  string  filename
 );
 
 import "DPI-C" function void memtrace_tick
 (
-    output bit     trace_read_valid,
+  output bit     trace_read_valid,
-    input  bit     trace_read_ready,
+  input  bit     trace_read_ready,
-    output longint trace_read_cycle,
+  output longint trace_read_cycle,
-    output longint trace_read_address
+  output longint trace_read_address,
+  output bit     trace_read_finished
 );
 
-module SimMemTrace  (
+module SimMemTrace #(parameter NUM_THREADS = 4) (
-    input              clock,
+  input              clock,
-    input              reset,
+  input              reset,
 
-    output                   trace_read_valid,
+  output                   trace_read_valid,
-    input                    trace_read_ready,
+  input                    trace_read_ready,
-    output [`DATA_WIDTH-1:0] trace_read_cycle,
+  output [`DATA_WIDTH-1:0] trace_read_cycle,
-    output [`DATA_WIDTH-1:0] trace_read_address
+  output [`DATA_WIDTH*NUM_THREADS-1:0] trace_read_address,
+  output                   trace_read_finished
 );
+  bit __in_valid;
+  longint __in_cycle;
+  longint __in_address[NUM_THREADS-1:0];
+  bit __in_finished;
+  string __uartlog;
+  int __uartno;
 
-    bit __in_valid;
+  initial begin
-    longint __in_cycle;
+      /* $value$plusargs("uartlog=%s", __uartlog); */
-    longint __in_address;
+      memtrace_init("vecadd.core1.thread4.trace");
-    string __uartlog;
+  end
-    int __uartno;
 
-    initial begin
+  reg __in_valid_reg;
-        $value$plusargs("uartlog=%s", __uartlog);
+  reg [`DATA_WIDTH-1:0] __in_cycle_reg;
-        memtrace_init("vecadd.core1.thread4.trace");
+  reg [`DATA_WIDTH-1:0] __in_address_reg [NUM_THREADS-1:0];
+  reg __in_finished_reg;
+
+  genvar g;
+
+  assign trace_read_valid    = __in_valid_reg;
+  assign trace_read_cycle    = __in_cycle_reg;
+  generate
+    for (g = 0; g < NUM_THREADS; g = g + 1) begin
+      assign trace_read_address[`DATA_WIDTH*(g+1)-1:`DATA_WIDTH*g]  = __in_address_reg[g];
     end
+  endgenerate
+  assign trace_read_finished = __in_finished_reg;
 
-    reg __in_valid_reg;
+  // Evaluate the signals on the positive edge
-    reg [`DATA_WIDTH-1:0] __in_cycle_reg;
+  always @(posedge clock) begin
-    reg [`DATA_WIDTH-1:0] __in_address_reg;
+    if (reset) begin
+      __in_valid = 1'b0;
+      __in_cycle = `DATA_WIDTH'b0;
+      for (integer i = 0; i < NUM_THREADS; i = i + 1) begin
+        __in_address[i] = `DATA_WIDTH'b0;
+      end
+      __in_finished = 1'b0;
 
-    assign trace_read_valid   = __in_valid_reg;
+      __in_valid_reg <= 1'b0;
-    assign trace_read_cycle   = __in_cycle_reg;
+      __in_cycle_reg <= `DATA_WIDTH'b0;
-    assign trace_read_address = __in_address_reg;
+      for (integer i = 0; i < NUM_THREADS; i = i + 1) begin
+        __in_address_reg[i] <= `DATA_WIDTH'b0;
+      end
+      __in_finished_reg <= 1'b0;
+    end else begin
+      for (integer i = 0; i < NUM_THREADS; i = i + 1) begin
+        memtrace_tick(
+          __in_valid,
+          trace_read_ready,
+          __in_cycle,
+          __in_address[i],
+          __in_finished
+        );
+      end
 
-    // Evaluate the signals on the positive edge
+      __in_valid_reg   <= __in_valid;
-    always @(posedge clock) begin
+      __in_cycle_reg   <= __in_cycle;
-        if (reset) begin
+      for (integer i = 0; i < NUM_THREADS; i = i + 1) begin
-            __in_valid = 1'b0;
+        __in_address_reg[i] <= __in_address[i];
-
+      end
-            __in_valid_reg <= 1'b0;
+      __in_finished_reg <= __in_finished;
-            __in_cycle_reg <= `DATA_WIDTH'b0;
-        end else begin
-            memtrace_tick(
-                __in_valid,
-                trace_read_ready,
-                __in_cycle,
-                __in_address
-            );
-
-            __in_valid_reg   <= __in_valid;
-            __in_cycle_reg   <= __in_cycle;
-            __in_address_reg <= __in_address;
-        end
     end
-
+  end
 endmodule

src/main/scala/tilelink/Coalescing.scala

@@ -39,7 +39,7 @@ class MemTraceDriver(implicit p: Parameters) extends LazyModule {
 
   lazy val module = new Impl
   class Impl extends LazyModuleImp(this) with UnitTestModule {
-    val sim = Module(new SimMemTrace)
+    val sim = Module(new SimMemTrace(2))
     sim.io.clock := clock
     sim.io.reset := reset.asBool
     sim.io.trace_read.ready := true.B
@@ -49,11 +49,13 @@ class MemTraceDriver(implicit p: Parameters) extends LazyModule {
     }
 
     // we're finished when there is no more memtrace to read
-    io.finished := !sim.io.trace_read.valid
+    io.finished := sim.io.trace_read.finished
   }
 }
 
-class SimMemTrace extends BlackBox with HasBlackBoxResource {
+class SimMemTrace(num_threads: Int)
+    extends BlackBox(Map("NUM_THREADS" -> num_threads))
+    with HasBlackBoxResource {
   val io = IO(new Bundle {
     val clock = Input(Clock())
     val reset = Input(Bool())
@@ -62,12 +64,14 @@ class SimMemTrace extends BlackBox with HasBlackBoxResource {
       val valid = Output(Bool())
       val ready = Input(Bool())
       val cycle = Output(UInt(64.W))
-      val address = Output(UInt(64.W))
+      val address = Output(UInt((64 * num_threads).W))
+      val finished = Output(Bool())
     }
   })
 
   addResource("/vsrc/SimMemTrace.v")
   addResource("/csrc/SimMemTrace.cc")
+  addResource("/csrc/SimMemTrace.h")
 }
 
 class CoalescingUnitTest(txns: Int = 5000, timeout: Int = 500000)(implicit