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Use edge.hasData instead of TLUtils in adapter

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This commit is contained in:
Hansung Kim
2023-10-25 20:28:01 -07:00
parent 1e8cc5ef90
commit 6371cdc03c
1 changed files with 8 additions and 16 deletions
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24
src/main/scala/tile/VortexTile.scala
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@@ -367,9 +367,7 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
outer.sourceWidth, outer.sourceWidth,
chiselTypeOf(core.io.mem.get.a.bits), chiselTypeOf(core.io.mem.get.a.bits),
chiselTypeOf(core.io.mem.get.d.bits), chiselTypeOf(core.io.mem.get.d.bits),
chiselTypeOf(outer.memNode.out.head._1.a.bits), outer.memNode.out.head
chiselTypeOf(outer.memNode.out.head._1.d.bits),
outer.memNode.out.head._2
)) ))
// connection: VortexBundle <--> VortexTLAdapter <--> TL memNode // connection: VortexBundle <--> VortexTLAdapter <--> TL memNode
@@ -382,9 +380,7 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
outer.sourceWidth, outer.sourceWidth,
chiselTypeOf(core.io.imem.get(0).a.bits), chiselTypeOf(core.io.imem.get(0).a.bits),
chiselTypeOf(core.io.imem.get(0).d.bits), chiselTypeOf(core.io.imem.get(0).d.bits),
chiselTypeOf(outer.imemNodes.head.out.head._1.a.bits), outer.imemNodes.head.out.head
chiselTypeOf(outer.imemNodes.head.out.head._1.d.bits),
outer.imemNodes.head.out.head._2
)) ))
// TODO: make imemNodes not a vector // TODO: make imemNodes not a vector
imemTLAdapter.io.inReq <> core.io.imem.get(0).a imemTLAdapter.io.inReq <> core.io.imem.get(0).a
@@ -405,9 +401,7 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
outer.sourceWidth, outer.sourceWidth,
chiselTypeOf(core.io.dmem.get(0).a.bits), chiselTypeOf(core.io.dmem.get(0).a.bits),
chiselTypeOf(core.io.dmem.get(0).d.bits), chiselTypeOf(core.io.dmem.get(0).d.bits),
chiselTypeOf(dmemTLBundles.head.a.bits), outer.dmemNodes(0).out.head
chiselTypeOf(dmemTLBundles.head.d.bits),
outer.dmemNodes(0).out.head._2
)) ))
} }
@@ -465,17 +459,16 @@ class VortexTLAdapter(
newSourceWidth: Int, newSourceWidth: Int,
inReqT: VortexBundleA, inReqT: VortexBundleA,
inRespT: VortexBundleD, inRespT: VortexBundleD,
outReqT: TLBundleA, outTL: (TLBundle, TLEdge)
outRespT: TLBundleD,
edge: TLEdge
) extends Module { ) extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
// in/out means upstream/downstream // in/out means upstream/downstream
val inReq = Flipped(Decoupled(inReqT)) val inReq = Flipped(Decoupled(inReqT))
val outReq = Decoupled(outReqT) val outReq = chiselTypeOf(outTL._1.a)
val inResp = Decoupled(inRespT) val inResp = Decoupled(inRespT)
val outResp = Flipped(Decoupled(outRespT)) val outResp = chiselTypeOf(outTL._1.d)
}) })
val edge = outTL._2
val sourceGen = Module(new SourceGenerator( val sourceGen = Module(new SourceGenerator(
newSourceWidth, newSourceWidth,
Some(inReqT.source), Some(inReqT.source),
@@ -501,8 +494,7 @@ class VortexTLAdapter(
io.inReq.ready := io.outReq.ready io.inReq.ready := io.outReq.ready
// VortexBundleD <> TLBundleD // VortexBundleD <> TLBundleD
// Do not reply to write requests; Vortex core does not expect ack on writes // Do not reply to write requests; Vortex core does not expect ack on writes
io.inResp.valid := io.outResp.valid && io.inResp.valid := io.outResp.valid && edge.hasData(io.outResp.bits)
!TLUtils.DOpcodeIsStore(io.outResp.bits.opcode, false.B)
io.inResp.bits.opcode := io.outResp.bits.opcode io.inResp.bits.opcode := io.outResp.bits.opcode
io.inResp.bits.size := io.outResp.bits.size io.inResp.bits.size := io.outResp.bits.size
io.inResp.bits.source := io.outResp.bits.source io.inResp.bits.source := io.outResp.bits.source