diff --git a/src/main/scala/rocket/VortexFatBank.scala b/src/main/scala/rocket/VortexFatBank.scala
index f54e087..9523743 100644
--- a/src/main/scala/rocket/VortexFatBank.scala
+++ b/src/main/scala/rocket/VortexFatBank.scala
@@ -23,6 +23,7 @@ case class L1SystemConfig(
     coreTagWidth: Int,
     writeInfoReqQSize: Int,
     mshrSize: Int,
+    l2ReqSourceGenSize: Int,
     uncachedAddrSets: Seq[AddressSet],
     icacheInstAddrSets: Seq[AddressSet]
 ) {
@@ -38,6 +39,7 @@ object defaultL1SystemConfig extends L1SystemConfig(
     coreTagWidth = 8,
     writeInfoReqQSize = 16,
     mshrSize = 8,
+    l2ReqSourceGenSize = 8,
     uncachedAddrSets = Seq(AddressSet(0x2000000L, 0xFFL)),
     icacheInstAddrSets = Seq(AddressSet(0x80000000L, 0xFFFFFFFL))
 )
@@ -59,6 +61,7 @@ class L1System (config:L1SystemConfig) (implicit p: Parameters) extends LazyModu
     val dmemXbar    = LazyModule(new TLXbar)
     dcache_banks.foreach { _.coalToVxCacheNode :=* dmemXbar.node}
     passThrough.coalToVxCacheNode :=* dmemXbar.node
+    icache_bank.coalToVxCacheNode :=* dmemXbar.node
 
     //L1System exposes to downstream as one tileLink Identity Node
     val L1SystemToL2Node = TLIdentityNode()
@@ -71,13 +74,15 @@ class L1System (config:L1SystemConfig) (implicit p: Parameters) extends LazyModu
 }
 
 
+//To-Do
+//Make the FatBank Pass Through a Blocking Module
 class FatBankPassThrough(config:L1SystemConfig) (implicit p: Parameters) extends LazyModule {
 
     val clientParam = Seq(TLMasterPortParameters.v1(
         clients = Seq(
             TLMasterParameters.v1(
                 name = "VortexFatBank",
-                sourceId = IdRange(0, 1 << 14), // FIXME: magic number
+                sourceId = IdRange(0, 1 << (log2Ceil(config.l2ReqSourceGenSize)+5) ),
                 supportsProbe = TransferSizes(1, config.wordSize),
                 supportsGet = TransferSizes(1, config.wordSize),
                 supportsPutFull = TransferSizes(1, config.wordSize),
@@ -128,8 +133,8 @@ class VortexFatBank (config: L1SystemConfig, bankId: Int, isICache: Boolean = fa
     def generateAddressSets(): Seq[AddressSet] = {
         
         if (isICache){
-            //config.icacheInstAddrSets
-            Seq(AddressSet(0x00000000L, 0xFFFFFFFFL))
+            config.icacheInstAddrSets
+            //Seq(AddressSet(0x00000000L, 0xFFFFFFFFL))
         } else {
             //suppose have 4 bank
             //base for bank 1: ...000000|01|0000
@@ -150,7 +155,7 @@ class VortexFatBank (config: L1SystemConfig, bankId: Int, isICache: Boolean = fa
         clients = Seq(
             TLMasterParameters.v1(
                 name = "VortexFatBank",
-                sourceId = IdRange(0, 1 << 14), // FIXME: magic number
+                sourceId = IdRange(0, config.l2ReqSourceGenSize), 
                 supportsProbe = TransferSizes(1, config.wordSize),
                 supportsGet = TransferSizes(1, config.wordSize),
                 supportsPutFull = TransferSizes(1, config.wordSize),
@@ -318,7 +323,11 @@ class VortexFatBankImp (
     //Therefore, we need our own internal source_ID generator for all write operation
     
 
-    val sourceGen = Module( new NewSourceGenerator(3, metadata = Some(UInt(32.W)), ignoreInUse = false))
+    val sourceGen = Module( new NewSourceGenerator(
+        log2Ceil(config.l2ReqSourceGenSize), 
+        metadata = Some(UInt(32.W)), 
+        ignoreInUse = false)
+        )
     
 
 
diff --git a/src/main/scala/tile/VortexTile.scala b/src/main/scala/tile/VortexTile.scala
index 5bbf8b5..d8d406b 100644
--- a/src/main/scala/tile/VortexTile.scala
+++ b/src/main/scala/tile/VortexTile.scala
@@ -236,16 +236,19 @@ class VortexTile private (
 
           //Connect L1System with imem_fetch_interface without XBar
           //coalToVxCacheNode is a bad naming, it really means up steam of vxBank in whihc it takes input
-          imemNodes.foreach { L1System.icache_bank.coalToVxCacheNode := TLWidthWidget(4) := _ }
+
+          //imemNodes.foreach { L1System.icache_bank.coalToVxCacheNode := TLWidthWidget(4) := _ }
+          imemNodes.foreach { L1System.dmemXbar.node := TLWidthWidget(4) := _ }
 
           //connect L1System with dmem_req from coalescer
           L1System.dmemXbar.node :=* coal.aggregateNode
 
+
           //L1System appears to downstream as one Identity Node
           L1System.L1SystemToL2Node
           
         }
-        
+
         case None => {
           imemNodes.foreach { tlMasterXbar.node := TLWidthWidget(4) := _ } //need to bind imem directly if not using FatBank
           coal.aggregateNode //if no fatbank, simply return coalescer.aggregateNode
diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala
index 49fea68..b008932 100644
--- a/src/main/scala/tilelink/Coalescing.scala
+++ b/src/main/scala/tilelink/Coalescing.scala
@@ -56,7 +56,7 @@ object DefaultInFlightTableSizeEnum extends InFlightTableSizeEnum {
 case class CoalescerConfig(
   enable: Boolean,        // globally enable or disable coalescing
   numLanes: Int,          // number of lanes (or threads) in a warp
-  reqQueueDepth: Int,        // request window per lane
+  reqQueueDepth: Int,     // request window per lane
   waitTimeout: Int,       // max cycles to wait before forced fifo dequeue, per lane
   addressWidth: Int,      // assume <= 32
   dataBusWidth: Int,      // memory-side downstream TileLink data bus size.  Nominally, this has
@@ -1367,7 +1367,8 @@ object TLUtils {
     // 0: PutFullData, 1: PutPartialData, 4: Get
     when(checkOpcode) {
       assert(
-        opcode === TLMessages.PutFullData || opcode === TLMessages.Get,
+        opcode === TLMessages.PutFullData || opcode === TLMessages.PutPartialData ||
+        opcode === TLMessages.Get,
         "unhandled TL A opcode found"
       )
     }