From 54a3e3cf72de3f20bb7b24aa307af8a04b7aa9d9 Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Mon, 8 May 2023 14:34:52 -0700
Subject: [PATCH] Initiate memtrace DPI only when trace_read_ready

This is required because otherwise we might overwrite into
the Verilog registers that contain a valid trace line that
was missed by downstream when it was not ready.  Basically
whenever trace_read_cycle stalls, we also want to stall
__in_* registers.
---
 src/main/resources/vsrc/SimMemTrace.v | 31 ++++++++++++++++-----------
 1 file changed, 18 insertions(+), 13 deletions(-)

diff --git a/src/main/resources/vsrc/SimMemTrace.v b/src/main/resources/vsrc/SimMemTrace.v
index fea2bed..74594cb 100644
--- a/src/main/resources/vsrc/SimMemTrace.v
+++ b/src/main/resources/vsrc/SimMemTrace.v
@@ -76,21 +76,26 @@ module SimMemTrace #(parameter FILENAME = "undefined", NUM_LANES = 4) (
       end
       __in_finished = 1'b0;
     end else begin
-      for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin
-        memtrace_query(
-          trace_read_ready,
-          trace_read_cycle,
-          tid,
+      // We have to write to __in_ regs only when trace_read_ready, or
+      // otherwise we might overwrite lines that were previously valid
+      // but the downstream missed by being not ready.
+      if (trace_read_ready) begin
+        for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin
+          memtrace_query(
+            trace_read_ready,
+            trace_read_cycle,
+            tid,
 
-          __in_valid[tid],
-          __in_address[tid],
- 
-          __in_is_store[tid],
-          __in_size[tid],
-          __in_data[tid],
+            __in_valid[tid],
+            __in_address[tid],
 
-          __in_finished
-        );
+            __in_is_store[tid],
+            __in_size[tid],
+            __in_data[tid],
+
+            __in_finished
+          );
+        end
       end
     end
   end