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Instantiate separate VortexL1Cache for imem and dmem

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This commit is contained in:
Hansung Kim
2023-11-28 19:22:11 -08:00
parent 0d60180d0d
commit 4efe9cb93f
1 changed files with 19 additions and 11 deletions
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30
src/main/scala/tile/VortexTile.scala
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@@ -271,7 +271,7 @@ class VortexTile private (
} }
// Conditionally instantiate L1 cache // Conditionally instantiate L1 cache
val l1Node = p(VortexL1Key) match { val (icacheNode, dcacheNode): (TLNode, TLNode) = p(VortexL1Key) match {
case Some(vortexL1Config) => { case Some(vortexL1Config) => {
println( println(
s"============ Using Vortex L1 cache =================" s"============ Using Vortex L1 cache ================="
@@ -281,22 +281,29 @@ class VortexTile private (
"Vortex L1 configuration currently only works when coalescer is also enabled." "Vortex L1 configuration currently only works when coalescer is also enabled."
) )
val l1cache = LazyModule(new VortexL1Cache(vortexL1Config)) val icache = LazyModule(new VortexL1Cache(vortexL1Config))
// // Connect L1 with imem_fetch_interface without XBar val dcache = LazyModule(new VortexL1Cache(vortexL1Config))
// // imemNodes.foreach { l1cache.icache_bank.coresideNode := TLWidthWidget(4) := _ } // imemNodes.foreach { icache.coresideNode := TLWidthWidget(4) := _ }
// imemNodes.foreach { l1cache.coresideNode := TLWidthWidget(4) := _ } assert(imemNodes.length == 1) // FIXME
icache.coresideNode := TLWidthWidget(4) := imemNodes(0)
// dmemNodes go through coalescerNode // dmemNodes go through coalescerNode
l1cache.coresideNode :=* coalescerNode dcache.coresideNode :=* coalescerNode
l1cache.masterNode (icache.masterNode, dcache.masterNode)
}
case None => {
val imemWideNode = TLIdentityNode()
assert(imemNodes.length == 1) // FIXME
imemWideNode := TLWidthWidget(4) := imemNodes(0)
(imemWideNode, coalescerNode)
} }
case None => coalescerNode
} }
if (vortexParams.useVxCache) { if (vortexParams.useVxCache) {
tlMasterXbar.node := TLWidthWidget(16) := memNode tlMasterXbar.node := TLWidthWidget(16) := memNode
} else { } else {
imemNodes.foreach { tlMasterXbar.node := TLWidthWidget(4) := _ } // imemNodes.foreach { tlMasterXbar.node := TLWidthWidget(4) := _ }
tlMasterXbar.node :=* l1Node tlMasterXbar.node :=* icacheNode
tlMasterXbar.node :=* dcacheNode
} }
/* below are copied from rocket */ /* below are copied from rocket */
@@ -584,7 +591,8 @@ class VortexTLAdapter(
io.outReq.bits.address := io.inReq.bits.address io.outReq.bits.address := io.inReq.bits.address
// Get requires contiguous mask; only copy core's potentially-partial mask // Get requires contiguous mask; only copy core's potentially-partial mask
// when writing // when writing
io.outReq.bits.mask := Mux(edge.hasData(io.outReq.bits), io.outReq.bits.mask := Mux(
edge.hasData(io.outReq.bits),
io.inReq.bits.mask, io.inReq.bits.mask,
// generate TL-correct mask // generate TL-correct mask
edge.mask(io.inReq.bits.address, io.inReq.bits.size) edge.mask(io.inReq.bits.address, io.inReq.bits.size)