From 4eb9973b2c90d2b4b4cf168fb5a8c12986f4151c Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Wed, 29 Nov 2023 15:13:17 -0800 Subject: [PATCH] Attempt to replicate bitwidth logic for dmem/imem tag --- src/main/scala/rocket/VortexCore.scala | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/main/scala/rocket/VortexCore.scala b/src/main/scala/rocket/VortexCore.scala index f956523..efb4c3e 100644 --- a/src/main/scala/rocket/VortexCore.scala +++ b/src/main/scala/rocket/VortexCore.scala @@ -40,14 +40,20 @@ class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle val reset_vector = Input(UInt(resetVectorLen.W)) val interrupts = Input(new CoreInterrupts()) + // TODO: parametrize + val NW_WIDTH = 1 + val uuidWidth = 44 + val imemTagWidth = uuidWidth + NW_WIDTH + val dmemTagWidth = 46 // FIXME: hardcoded; see gpu_pkg.sv + // conditionally instantiate ports depending on whether we want to use VX_cache or not val imem = if (!tile.vortexParams.useVxCache) Some(Vec(1, new Bundle { - val a = Decoupled(new VortexBundleA(tagWidth = 46, dataWidth = 32)) - val d = Flipped(Decoupled(new VortexBundleD(tagWidth = 46, dataWidth = 32))) + val a = Decoupled(new VortexBundleA(tagWidth = imemTagWidth, dataWidth = 32)) + val d = Flipped(Decoupled(new VortexBundleD(tagWidth = imemTagWidth, dataWidth = 32))) })) else None val dmem = if (!tile.vortexParams.useVxCache) Some(Vec(tile.numLanes, new Bundle { - val a = Decoupled(new VortexBundleA(tagWidth = 46, dataWidth = 32)) - val d = Flipped(Decoupled(new VortexBundleD(tagWidth = 46, dataWidth = 32))) + val a = Decoupled(new VortexBundleA(tagWidth = dmemTagWidth, dataWidth = 32)) + val d = Flipped(Decoupled(new VortexBundleD(tagWidth = dmemTagWidth, dataWidth = 32))) })) else None val mem = if (tile.vortexParams.useVxCache) Some(new Bundle { val a = Decoupled(new VortexBundleA(tagWidth = 15, dataWidth = 128))