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coalReqT source width bug fix

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This commit is contained in:
Richard Yan
2023-05-05 23:02:25 -07:00
parent bb6105a0c7
commit 457b67a8d4
1 changed files with 2 additions and 3 deletions
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5
src/main/scala/tilelink/Coalescing.scala
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@@ -247,8 +247,7 @@ class CoalShiftQueue[T <: Data](gen: T, entries: Int, config: CoalescerConfig) e
// dequeue is valid when: // dequeue is valid when:
// head entry is valid, has not been processed by downstream, and is not coalescable // head entry is valid, has not been processed by downstream, and is not coalescable
deq.bits := elts.map(_.head.bits)(i) deq.bits := elts.map(_.head.bits)(i)
deq.valid := elts.map(_.head.valid)(i) && !deqDone(i) && deq.valid := elts.map(_.head.valid)(i) && !deqDone(i) && !io.coalescable(i)
(!io.invalidate.valid || !io.coalescable(i))
// can take new entries if not empty, or if full but shifting // can take new entries if not empty, or if full but shifting
enq.ready := (!ctrl.full) || ctrl.shift enq.ready := (!ctrl.full) || ctrl.shift
@@ -566,7 +565,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
val reqQueueEntryT = new ReqQueueEntry(sourceWidth, config.wordWidth, config.addressWidth, config.wordSizeInBytes) val reqQueueEntryT = new ReqQueueEntry(sourceWidth, config.wordWidth, config.addressWidth, config.wordSizeInBytes)
val reqQueues = Module(new CoalShiftQueue(reqQueueEntryT, config.queueDepth, config)) val reqQueues = Module(new CoalShiftQueue(reqQueueEntryT, config.queueDepth, config))
val coalReqT = new ReqQueueEntry(sourceWidth, log2Ceil(config.maxCoalLogSize), val coalReqT = new ReqQueueEntry(log2Ceil(config.numNewSrcIds), log2Ceil(config.maxCoalLogSize),
config.addressWidth, config.maxCoalLogSize) config.addressWidth, config.maxCoalLogSize)
val coalescer = Module(new MultiCoalescer(reqQueues, coalReqT, config)) val coalescer = Module(new MultiCoalescer(reqQueues, coalReqT, config))
coalescer.io.window := reqQueues.io coalescer.io.window := reqQueues.io