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bump verilog sources, remove files and mem changes

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This commit is contained in:
Richard Yan
2023-09-09 01:55:02 -07:00
parent 8cef2ae135
commit 43f95175f1
3 changed files with 26 additions and 18 deletions
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2
src/main/resources/vsrc/vortex

Submodule src/main/resources/vsrc/vortex updated: 2dbc5bffcd...7d0d38ca6c

30
src/main/scala/rocket/VortexCore.scala
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@@ -16,20 +16,20 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
extends BlackBox with HasBlackBoxResource { extends BlackBox with HasBlackBoxResource {
// addResource("/vsrc/vortex/hw/unit_tests/generic_queue/testbench.v") // addResource("/vsrc/vortex/hw/unit_tests/generic_queue/testbench.v")
// addResource("/vsrc/vortex/hw/unit_tests/VX_divide_tb.v") // addResource("/vsrc/vortex/hw/unit_tests/VX_divide_tb.v")
addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0_rtl.v") // addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0_rtl.v")
addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v") // addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v")
addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0.v") // addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0.v")
addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_rtl.v") // addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0_rtl.v")
addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1_rtl.v") // addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1_rtl.v")
addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1.v") // addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1.v")
addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v") // addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v")
addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1_rtl.v") // addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1_rtl.v")
addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v") // addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v")
addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v") // addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v")
addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_rtl.v") // addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_rtl.v")
addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_rtl.v") // addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_rtl.v")
addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v") // addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v")
addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v") // addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v")
// addResource("/vsrc/vortex/hw/syn/modelsim/vortex_tb.v") // addResource("/vsrc/vortex/hw/syn/modelsim/vortex_tb.v")
addResource("/vsrc/vortex/hw/rtl/VX_dispatch.sv") addResource("/vsrc/vortex/hw/rtl/VX_dispatch.sv")
addResource("/vsrc/vortex/hw/rtl/VX_issue.sv") addResource("/vsrc/vortex/hw/rtl/VX_issue.sv")
@@ -123,7 +123,7 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
addResource("/vsrc/vortex/hw/VX_config.h") addResource("/vsrc/vortex/hw/VX_config.h")
addResource("/vsrc/vortex/sim/common/rvfloats.h") addResource("/vsrc/vortex/sim/common/rvfloats.h")
addResource("/vsrc/vortex/sim/common/rvfloats.cpp") addResource("/vsrc/vortex/sim/common/rvfloats.cpp")
addResource("/csrc/softfloat.a") // addResource("/csrc/softfloat_archive.a")
addResource("/csrc/softfloat/include/internals.h") addResource("/csrc/softfloat/include/internals.h")
addResource("/csrc/softfloat/include/primitives.h") addResource("/csrc/softfloat/include/primitives.h")
addResource("/csrc/softfloat/include/primitiveTypes.h") addResource("/csrc/softfloat/include/primitiveTypes.h")

12
src/main/scala/tile/VortexTile.scala
View File

@@ -91,14 +91,22 @@ class VortexTile private(
val imemNode = TLClientNode(Seq(TLMasterPortParameters.v1( val imemNode = TLClientNode(Seq(TLMasterPortParameters.v1(
clients = Seq(TLMasterParameters.v1( clients = Seq(TLMasterParameters.v1(
sourceId = IdRange(0, 1 << 8), // TODO magic number sourceId = IdRange(0, 1 << 8), // TODO magic number
name = s"Vortex Core I-Mem" name = s"Vortex Core I-Mem",
requestFifo = true,
supportsProbe = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
supportsGet = TransferSizes(1, lazyCoreParamsView.coreDataBytes)
)) ))
))) )))
val dmemNode = TLClientNode(Seq(TLMasterPortParameters.v1( val dmemNode = TLClientNode(Seq(TLMasterPortParameters.v1(
clients = Seq(TLMasterParameters.v1( clients = Seq(TLMasterParameters.v1(
sourceId = IdRange(0, 1 << 8), // TODO magic number sourceId = IdRange(0, 1 << 8), // TODO magic number
name = s"Vortex Core D-Mem" name = s"Vortex Core D-Mem",
requestFifo = true,
supportsProbe = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
supportsGet = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
supportsPutFull = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
supportsPutPartial = TransferSizes(1, lazyCoreParamsView.coreDataBytes)
)) ))
))) )))