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bump verilog sources, remove files and mem changes

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This commit is contained in:
Richard Yan
2023-09-09 01:55:02 -07:00
parent 8cef2ae135
commit 43f95175f1
3 changed files with 26 additions and 18 deletions
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12
src/main/scala/tile/VortexTile.scala
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@@ -91,14 +91,22 @@ class VortexTile private(
val imemNode = TLClientNode(Seq(TLMasterPortParameters.v1(
clients = Seq(TLMasterParameters.v1(
sourceId = IdRange(0, 1 << 8), // TODO magic number
name = s"Vortex Core I-Mem"
name = s"Vortex Core I-Mem",
requestFifo = true,
supportsProbe = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
supportsGet = TransferSizes(1, lazyCoreParamsView.coreDataBytes)
))
)))
val dmemNode = TLClientNode(Seq(TLMasterPortParameters.v1(
clients = Seq(TLMasterParameters.v1(
sourceId = IdRange(0, 1 << 8), // TODO magic number
name = s"Vortex Core D-Mem"
name = s"Vortex Core D-Mem",
requestFifo = true,
supportsProbe = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
supportsGet = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
supportsPutFull = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
supportsPutPartial = TransferSizes(1, lazyCoreParamsView.coreDataBytes)
))
)))