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queued cisc commands

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This commit is contained in:
Richard Yan
2024-09-09 22:38:16 -07:00
parent 06edba2a78
commit 3fd0fd296b
1 changed files with 7 additions and 2 deletions
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9
src/main/scala/radiance/tile/GemminiTile.scala
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@@ -169,7 +169,13 @@ class GemminiTileModuleImp(outer: GemminiTile) extends BaseTileModuleImp(outer)
} }
val ciscInst = Wire(ciscInstT) val ciscInst = Wire(ciscInstT)
when (accSlave.cmd.valid) { val accCommandQueue = Module(new Queue(UInt(32.W), 4, false, true))
accCommandQueue.io.enq.bits := accSlave.cmd.bits
accCommandQueue.io.enq.valid := accSlave.cmd.valid
accCommandQueue.io.deq.ready := !ciscValid
assert(!accSlave.cmd.valid || accCommandQueue.io.enq.ready, "cisc command queue full")
when (accCommandQueue.io.deq.fire) {
ciscValid := true.B ciscValid := true.B
ciscId := accSlave.cmd.bits(7, 0) ciscId := accSlave.cmd.bits(7, 0)
ciscArgs := accSlave.cmd.bits(31, 8) ciscArgs := accSlave.cmd.bits(31, 8)
@@ -207,7 +213,6 @@ class GemminiTileModuleImp(outer: GemminiTile) extends BaseTileModuleImp(outer)
println(s"gemmini cisc initialized with DIM=${config.DIM}, tileSize=${tileSizeM},${tileSizeN},${tileSizeK}") println(s"gemmini cisc initialized with DIM=${config.DIM}, tileSize=${tileSizeM},${tileSizeN},${tileSizeK}")
println(f"boundsInst=${rectBoundsInst.litValue}%x, quartile=${spadQuartile}") println(f"boundsInst=${rectBoundsInst.litValue}%x, quartile=${spadQuartile}")
when (ciscValid) { when (ciscValid) {
assert(!accSlave.cmd.valid, "cisc state machine already busy")
switch (ciscId(6, 0)) { switch (ciscId(6, 0)) {
is (0.U) { is (0.U) {
ciscInst := microcodeEntry(Seq(boundsInst, ciscInst := microcodeEntry(Seq(boundsInst,