diff --git a/radiance.mk b/radiance.mk
index 344ee54..d5a5552 100644
--- a/radiance.mk
+++ b/radiance.mk
@@ -2,18 +2,19 @@
 # extra variables/targets ingested by the chipyard make system
 ##############################################################
 
+RADPIE_SRC_DIR = $(base_dir)/generators/radiance/radpie
+RADPIE_BUILD_DIR = $(RADPIE_SRC_DIR)/target/release
+
 ##################################################################
 # THE FOLLOWING MUST BE += operators
 ##################################################################
 
-RADPIE_SRC_DIR = $(base_dir)/generators/radiance/radpie
-RADPIE_BUILD_DIR = $(RADPIE_SRC_DIR)/target/release
-
 # EXTRA_SIM_REQS += radpie
 EXTRA_SIM_LDFLAGS += -L$(RADPIE_BUILD_DIR) -Wl,-rpath,$(RADPIE_BUILD_DIR) -lradpie
 EXTRA_SIM_PREPROC_DEFINES += \
 	+define+SIMULATION \
 	+define+GPR_RESET \
+	+define+GPR_DUPLICATED \
 	+define+LSU_DUP_DISABLE \
 	+define+DBG_TRACE_CORE_PIPELINE_VCS \
 	+define+PERF_ENABLE \
diff --git a/src/main/scala/radiance/tile/VortexCore.scala b/src/main/scala/radiance/tile/VortexCore.scala
index adb10a3..ba74508 100644
--- a/src/main/scala/radiance/tile/VortexCore.scala
+++ b/src/main/scala/radiance/tile/VortexCore.scala
@@ -176,6 +176,7 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters)
   addResource("/vsrc/vortex/hw/rtl/core/VX_lsu_unit.sv")
   addResource("/vsrc/vortex/hw/rtl/core/VX_muldiv_unit.sv")
   addResource("/vsrc/vortex/hw/rtl/core/VX_operands.sv")
+  addResource("/vsrc/vortex/hw/rtl/core/VX_operands_dup.sv")
   addResource("/vsrc/vortex/hw/rtl/core/VX_pending_instr.sv")
   addResource("/vsrc/vortex/hw/rtl/core/VX_schedule.sv")
   addResource("/vsrc/vortex/hw/rtl/core/VX_scoreboard.sv")