From 3a0fdb2c67809742952984b1c2632436dba284e3 Mon Sep 17 00:00:00 2001 From: Richard Yan Date: Tue, 25 Apr 2023 02:26:13 -0700 Subject: [PATCH] WIP diplomacy set up for coal unit test --- src/main/scala/tilelink/Coalescing.scala | 6 +- .../scala/coalescing/CoalescingUnitTest.scala | 104 +++++++++++++----- 2 files changed, 81 insertions(+), 29 deletions(-) diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala index 9e8e26e..b9a46ed 100644 --- a/src/main/scala/tilelink/Coalescing.scala +++ b/src/main/scala/tilelink/Coalescing.scala @@ -606,8 +606,12 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends newEntry.source := coalescer.io.out_req.bits.source // TODO: richard to write table fill logic + // FIXME: this assertion used to say 1 << config.MAX_SIZE + // I changed this to say DATA BUS SIZE. We need another assertion + // to assert that MAX_SIZE is <= DATA_BUS_SIZE because we do not support + // multi-beat writes currently assert( - tlCoal.params.dataBits == (1 << config.MAX_SIZE) * 8, + tlCoal.params.dataBits == (1 << config.DATA_BUS_SIZE) * 8, s"tlCoal param dataBits (${tlCoal.params.dataBits}) mismatch coalescer constant" ) val origReqs = reqQueues.map(q => q.io.queue.deq.bits) diff --git a/src/test/scala/coalescing/CoalescingUnitTest.scala b/src/test/scala/coalescing/CoalescingUnitTest.scala index 0a965b6..1d8bfcc 100644 --- a/src/test/scala/coalescing/CoalescingUnitTest.scala +++ b/src/test/scala/coalescing/CoalescingUnitTest.scala @@ -5,6 +5,8 @@ import chiseltest._ import org.scalatest.flatspec.AnyFlatSpec import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.MultiPortQueue +import freechips.rocketchip.diplomacy._ +import chipsalliance.rocketchip.config.Parameters class MultiPortQueueUnitTest extends AnyFlatSpec with ChiselScalatestTester { behavior of "MultiPortQueue" @@ -31,29 +33,75 @@ class MultiPortQueueUnitTest extends AnyFlatSpec with ChiselScalatestTester { } } +class DummyCoalescingUnitTB(implicit p: Parameters) extends LazyModule { + val cpuNodes = Seq.tabulate(testConfig.NUM_LANES) { _ => + TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( + name = "processor-nodes", + sourceId = IdRange(0, testConfig.NUM_OLD_IDS), + requestFifo = true, + visibility = Seq(AddressSet(0x0, 0xffffff))))))) // 24 bit address space (TODO probably use testConfig) + } + + val mitm = Seq.tabulate(testConfig.NUM_LANES) {_ => TLIdentityNode()} + + val device = new SimpleDevice("dummy", Seq("dummy")) + val beatBytes = 1 << testConfig.DATA_BUS_SIZE // 256 bit bus + val l2Nodes = Seq.tabulate(5) { _ => + TLManagerNode(Seq(TLSlavePortParameters.v1(Seq(TLManagerParameters( + address = Seq(AddressSet(0x0, 0xffffff)), // should be matching cpuNode + resources = device.reg, + regionType = RegionType.UNCACHED, + executable = true, + supportsArithmetic = TransferSizes(1, beatBytes), + supportsLogical = TransferSizes(1, beatBytes), + supportsGet = TransferSizes(1, beatBytes), + supportsPutFull = TransferSizes(1, beatBytes), + supportsPutPartial = TransferSizes(1, beatBytes), + supportsHint = TransferSizes(1, beatBytes), + fifoId = Some(0))), beatBytes))) + } + + val dut = LazyModule(new CoalescingUnit(testConfig)) + + lazy val module = new DummyCoalescingUnitTBImp(this) +} + +class DummyCoalescingUnitTBImp(outer: DummyCoalescingUnitTB) extends LazyModuleImp(outer) { + val mitmNodesImp = outer.mitm + val coal = outer.dut +} + class CoalescerUnitTest extends AnyFlatSpec with ChiselScalatestTester { behavior of "multi- and mono-coalescers" it should "coalesce fully consecutive accesses at size 4, only once" in { - test(new CoalescingUnit(testConfig)) { c => - val dut = c.module - val window = dut.reqQueues - val (nodes, _) = c.node.in.unzip + implicit val p: Parameters = Parameters.empty - def pokeA(idx: Int, op: Int, size: Int, source: Int, addr: Int, mask: Int, data: Int): Unit = { + val tb = LazyModule(new DummyCoalescingUnitTB()) +// val outer = LazyModule(new CoalescingUnit(testConfig)) + + val coal = tb.dut + tb.cpuNodes.zip(tb.mitm).foreach { case (a, b) => b := a } + tb.mitm.foreach(coal.node := _) + tb.l2Nodes.foreach(_ := coal.node) + + test(tb.module) { c => +// val nodes = c.cpuNodesImp.map(_.out.head._1) +// val nodes = c.coal.node.in.map(_._1) + val nodes = c.mitmNodesImp.map(_.in.head._1) + + def pokeA(nodes: Seq[TLBundle], idx: Int, op: Int, size: Int, source: Int, addr: Int, mask: Int, data: Int): Unit = { val node = nodes(idx) - node.a.ready.expect(true.B) - val bundle = Wire(new TLBundleA(node.a.bits.params)) - bundle.opcode := Mux(op.B, TLMessages.PutFullData, TLMessages.Get) - bundle.param := 0.U - bundle.size := size.U - bundle.source := source.U - bundle.address := addr.U - bundle.mask := mask.U - bundle.data := data.U - bundle.corrupt := false.B - node.a.bits.poke(bundle) - node.a.valid.poke(true.B) +// node.a.ready.expect(true.B) + node.a.bits.opcode.poke(if (op == 1) TLMessages.PutFullData else TLMessages.Get) + node.a.bits.param.poke(0.U) + node.a.bits.size.poke(size.U) + node.a.bits.source.poke(source.U) + node.a.bits.address.poke(addr.U) + node.a.bits.mask.poke(mask.U) + node.a.bits.data.poke(data.U) + node.a.bits.corrupt.poke(false.B) +// node.a.valid.poke(true.B) } def unsetA(): Unit = { @@ -63,17 +111,17 @@ class CoalescerUnitTest extends AnyFlatSpec with ChiselScalatestTester { } } - pokeA(idx=0, op=1, size=2, source=0, addr=0x10, mask=0xf, data=0x1111) - pokeA(idx=1, op=1, size=2, source=1, addr=0x14, mask=0xf, data=0x2222) - pokeA(idx=2, op=1, size=2, source=2, addr=0x18, mask=0xf, data=0x3333) - pokeA(idx=3, op=1, size=2, source=3, addr=0x1c, mask=0xf, data=0x4444) + pokeA(nodes, idx=0, op=1, size=2, source=0, addr=0x10, mask=0xf, data=0x1111) + pokeA(nodes, idx=1, op=1, size=2, source=1, addr=0x14, mask=0xf, data=0x2222) + pokeA(nodes, idx=2, op=1, size=2, source=2, addr=0x18, mask=0xf, data=0x3333) + pokeA(nodes, idx=3, op=1, size=2, source=3, addr=0x1c, mask=0xf, data=0x4444) - dut.clock.step() + c.clock.step() unsetA() - dut.clock.step() - dut.clock.step() + c.clock.step() + c.clock.step() } } @@ -325,18 +373,18 @@ class CoalShiftQueueTest extends AnyFlatSpec with ChiselScalatestTester { } object testConfig extends CoalescerConfig( - MAX_SIZE = 6, // maximum coalesced size + MAX_SIZE = 5, // maximum coalesced size DEPTH = 2, // request window per lane WAIT_TIMEOUT = 8, // max cycles to wait before forced fifo dequeue, per lane ADDR_WIDTH = 24, // assume <= 32 - DATA_BUS_SIZE = 4, // 2^4=16 bytes, 128 bit bus + DATA_BUS_SIZE = 5, // 2^5=32 bytes, 256 bit bus NUM_LANES = 4, // WATERMARK = 2, // minimum buffer occupancy to start coalescing WORD_SIZE = 4, // 32-bit system WORD_WIDTH = 2, // log(WORD_SIZE) - NUM_OLD_IDS = 16, // num of outstanding requests per lane, from processor + NUM_OLD_IDS = 16, // num of outstanding requests per lane, from processor NUM_NEW_IDS = 4, // num of outstanding coalesced requests - COAL_SIZES = Seq(4, 6), + COAL_SIZES = Seq(4, 5), SizeEnum = DefaultInFlightTableSizeEnum )